公开(公告)号：US07124283B2

公开(公告)日：2006-10-17

申请号：US10457409

申请日：2003-06-10

申请人： Tetsuya Yamada ,  Naohiko Irie ,  Takanobu Tsunoda ,  Takahiro Irita ,  Keisuke Toyama ,  Masayuki Kabasawa

发明人： Tetsuya Yamada ,  Naohiko Irie ,  Takanobu Tsunoda ,  Takahiro Irita ,  Keisuke Toyama ,  Masayuki Kabasawa

IPC分类号： G06F5/00

CPC分类号： G06F9/3879 ,  G06F9/30174 ,  G06F9/4552

摘要： The present invention provides a hardware accelerator, which allows faster switching between processing modes. In an information processing device with a bytecode accelerator BCA for translating a stack-based intermediate code (bytecode) into register-based instructions, a selector SEL for switching between BCA and soft VM is posed between an instruction part FET and a decode part DEC and data transfer paths P4 and P5 are formed between BCA and the register file REG_FILE. When bytecode accelerator BCA is activated, the P3 side is selected by the selector SEL and the translated CPU instructions are transferred to the decode part DEC. If the intermediate language code cannot be translated by the BCA, the processing mode is switched to software processing. During switching between the modes, internal information of BCA can be transferred between BCA and REG_FILE in parallel, achieving faster mode switching.

摘要翻译： 本发明提供一种硬件加速器，其允许在处理模式之间更快地切换。 在具有用于将基于堆栈的中间码（字节码）转换为基于寄存器的指令的字节码加速器BCA的信息处理装置中，在指令部分FET和解码部分DEC之间存在用于在BCA和软VM之间切换的选择器SEL， 在BCA和寄存器文件REG_FILE之间形成数据传送路径P 4和P 5。 当字节码加速器BCA被激活时，选择器SEL选择P 3侧，转换的CPU指令被传送到解码部分DEC。 如果BCA不能翻译中间语言代码，则将处理模式切换到软件处理。 在模式切换期间，BCA的内部信息可以在BCA和REG_FILE之间并行传输，实现更快的模式切换。

公开(公告)号：US07493479B2

公开(公告)日：2009-02-17

申请号：US10458289

申请日：2003-06-11

申请人： Masayuki Kabasawa ,  Naohiko Irie ,  Takahiro Irita ,  Tetsuya Yamada ,  Takanobu Tsunoda

发明人： Masayuki Kabasawa ,  Naohiko Irie ,  Takahiro Irita ,  Tetsuya Yamada ,  Takanobu Tsunoda

IPC分类号： G06F9/30 ,  G06F9/40 ,  G06F15/00 ,  G06F7/38

CPC分类号： G06F9/30174 ,  G06F9/3851

摘要： A method and apparatus are provided for event detection for a multiple instruction-set processor. In one example of the apparatus, a data processing device comprises an instruction execution device configured to execute a first instruction set as specific instructions; an instruction conversion circuit configured to convert instructions of a second instruction set into a first instruction string of the first instruction set, and further configured to supply the first instruction string to the instruction execution device; and a counter device configured to count a prescribed event, wherein the instruction conversion circuit is further configured to output a prescribed instruction when the counter device is satisfied by a prescribed condition.

摘要翻译： 提供了一种用于多指令集处理器的事件检测的方法和装置。 在该装置的一个示例中，数据处理装置包括被配置为执行第一指令集作为特定指令的指令执行装置; 指令转换电路，被配置为将第二指令集的指令转换为第一指令集的第一指令串，并且还被配置为将第一指令串提供给指令执行装置; 以及计数器装置，被配置为对规定的事件进行计数，其中所述指令转换电路还被配置为当所述计数器装置满足规定条件时输出规定的指令。

公开(公告)号：US20050027965A1

公开(公告)日：2005-02-03

申请号：US10883758

申请日：2004-07-06

申请人： Tetsuya Yamada ,  Naohiko Irie ,  Takahiro Irita ,  Masayuki Kabasawa

发明人： Tetsuya Yamada ,  Naohiko Irie ,  Takahiro Irita ,  Masayuki Kabasawa

IPC分类号： G06F9/38 ,  G06F9/30 ,  G06F9/302 ,  G06F9/318 ,  G06F9/45 ,  G06F15/00

CPC分类号： G06F9/30174 ,  G06F9/30014 ,  G06F9/3861 ,  G06F9/3877 ,  G06F9/3879

摘要： A hardware accelerator is used to execute a floating-point byte-code in an information processing device. For a floating-point byte-code, a byte-code accelerator BCA feeds an instruction stream for using a FPU to a CPU. When the FPU is used, first the data is transferred to the FPU register from a general-purpose register, and then an FPU operation is performed. For data, such as a denormalized number, that cannot be processed by the FPU, in order to call a floating-point math library of software, the processing of the BCA is completed and the processing moves to processing by software. In order to realize this, data on a data transfer bus from the CPU to the FPU is snooped by the hardware accelerator, and a cancel request is signaled to the CPU to inhibit execution of the FPU operation when 4corresponding data is detected in a data checking part.

摘要翻译： 硬件加速器用于在信息处理设备中执行浮点字节码。 对于浮点字节码，字节码加速器BCA将用于使用FPU的指令流馈送到CPU。 当使用FPU时，首先将数据从通用寄存器传送到FPU寄存器，然后执行FPU操作。 对于不能由FPU处理的数据，如非规范化数字，为了调用软件的浮点数学库，BCA的处理完成，并且处理转移到软件处理。 为了实现这一点，由硬件加速器监视从CPU到FPU的数据传输总线上的数据，并且当在数据检查中检测到4个对应数据时，向CPU发送取消请求以禁止执行FPU操作 部分。

公开(公告)号：US07788469B2

公开(公告)日：2010-08-31

申请号：US10883758

申请日：2004-07-06

申请人： Tetsuya Yamada ,  Naohiko Irie ,  Takahiro Irita ,  Masayuki Kabasawa

发明人： Tetsuya Yamada ,  Naohiko Irie ,  Takahiro Irita ,  Masayuki Kabasawa

IPC分类号： G06F15/76

CPC分类号： G06F9/30174 ,  G06F9/30014 ,  G06F9/3861 ,  G06F9/3877 ,  G06F9/3879

摘要： A hardware accelerator is used to execute a floating-point byte-code in an information processing device. For a floating-point byte-code, a byte-code accelerator BCA feeds an instruction stream for using a FPU to a CPU. When the FPU is used, first the data is transferred to the FPU register from a general-purpose register, and then an FPU operation is performed. For data, such as a denormalized number, that cannot be processed by the FPU, in order to call a floating-point math library of software, the processing of the BCA is completed and the processing moves to processing by software. In order to realize this, data on a data transfer bus from the CPU to the FPU is snooped by the hardware accelerator, and a cancel request is signaled to the CPU to inhibit execution of the FPU operation when corresponding data is detected in a data checking part.

摘要翻译： 硬件加速器用于在信息处理设备中执行浮点字节码。 对于浮点字节码，字节码加速器BCA将用于使用FPU的指令流馈送到CPU。 当使用FPU时，首先将数据从通用寄存器传送到FPU寄存器，然后执行FPU操作。 对于不能由FPU处理的数据，如非规范化数字，为了调用软件的浮点数学库，BCA的处理完成，并且处理转移到软件处理。 为了实现这一点，由硬件加速器窥探从CPU到FPU的数据传输总线上的数据，并且当在数据检查中检测到对应的数据时，向CPU发送取消请求以禁止执行FPU操作 部分。

公开(公告)号：US20060101427A1

公开(公告)日：2006-05-11

申请号：US11260423

申请日：2005-10-28

申请人： Tetsuya Yamada ,  Naohiko Irie

发明人： Tetsuya Yamada ,  Naohiko Irie

IPC分类号： G06F9/45 ,  G06F9/44

CPC分类号： G06F9/30174

摘要： A bytecode accelerator which translates stack-based intermediate language (bytecodes) into register-based CPU instructions transfers plural pieces of internal information from a register file of a CPU to the bytecode accelerator by means of an internal transfer bus between the bytecode accelerator-and the CPU and an input selection logic of the bytecode accelerator when the bytecode accelerator is started and transfers plural pieces of internal information in the bytecode accelerator to the register file of the CPU by means of the internal transfer bus, an output selector and an output selector selection logic of the bytecode accelerator when the bytecode accelerator ends its operation in transition between hardware processing and software processing by software virtual machine.

摘要翻译： 将基于堆栈的中间语言（字节码）转换为基于寄存器的CPU指令的字节码加速器通过字节码加速器和字节码加速器之间的内部传送总线将多条内部信息从CPU的寄存器文件传送到字节码加速器 CPU和字节码加速器的输入选择逻辑，并且通过内部传送总线，输出选择器和输出选择器选择将字节码加速器中的多条内部信息传送到CPU的寄存器文件 字节码加速器在硬件处理和软件虚拟机的软件处理之间的转换中结束其操作时，字节码加速器的逻辑。

公开(公告)号：US07853776B2

公开(公告)日：2010-12-14

申请号：US11260423

申请日：2005-10-28

申请人： Tetsuya Yamada ,  Naohiko Irie

发明人： Tetsuya Yamada ,  Naohiko Irie

IPC分类号： G06F9/30

CPC分类号： G06F9/30174

摘要： A bytecode accelerator which translates stack-based intermediate language (bytecodes) into register-based CPU instructions transfers plural pieces of internal information from a register file of a CPU to the bytecode accelerator by means of an internal transfer bus between the bytecode accelerator and the CPU and an input selection logic of the bytecode accelerator when the bytecode accelerator is started and transfers plural pieces of internal information in the bytecode accelerator to the register file of the CPU by means of the internal transfer bus, an output selector and an output selector selection logic of the bytecode accelerator when the bytecode accelerator ends its operation in transition between hardware processing and software processing by software virtual machine.

摘要翻译： 将基于堆栈的中间语言（字节码）转换为基于寄存器的CPU指令的字节码加速器通过字节码加速器和CPU之间的内部传输总线将多条内部信息从CPU的寄存器文件传送到字节码加速器 以及当字节代码加速器启动时字节码加速器的输入选择逻辑，并且通过内部传送总线，输出选择器和输出选择器选择逻辑，将字节码加速器中的多条内部信息传送到CPU的寄存器文件 字节码加速器在硬件处理和软件虚拟机的软件处理之间的转换中结束其操作。

公开(公告)号：US07340078B2

公开(公告)日：2008-03-04

申请号：US10876596

申请日：2004-06-28

申请人： Hiroaki Shikano ,  Naohiko Irie

发明人： Hiroaki Shikano ,  Naohiko Irie

IPC分类号： G06K9/00

CPC分类号： G06K9/00664

摘要： Disclosed here is an information processing system capable of recognizing actions and circumstances of a user with respect to both space and time as a “situation” to recognize the user's request using a plurality of sensing nodes that work cooperatively with each another, thereby responding autonomously to the user's request according to the recognition results. The plurality of sensing nodes and a responding device are disposed in a target space to build up a network for recognizing the situation in the target space. And, a plurality of recognition means are used to recognize the situation with respect to both space and time related to the existence of the user. And, an integral processing portion (master) is selected from among the plurality of sensing nodes, thereby dispersing the system load. If there are a plurality of users, the system can make recognition in accordance with the request of each of those users.

摘要翻译： 这里公开了一种信息处理系统，其能够将用户相对于空间和时间的动作和情况识别为使用多个彼此协作工作的感测节点来识别用户的请求的“情况”，从而自主地响应于 用户的请求根据识别结果。 多个感测节点和响应装置设置在目标空间中以构建用于识别目标空间中的情况的网络。 并且，使用多个识别装置来识别与用户的存在相关的空间和时间的情况。 并且，从多个感测节点中选择积分处理部（主），从而分散系统负载。 如果存在多个用户，则系统可以根据每个用户的请求进行识别。

公开(公告)号：US20070284619A1

公开(公告)日：2007-12-13

申请号：US11797034

申请日：2007-04-30

申请人： Yusuke Kanno ,  Hiroyuki Mizuno ,  Naohiko Irie

发明人： Yusuke Kanno ,  Hiroyuki Mizuno ,  Naohiko Irie

IPC分类号： H01L29/73

CPC分类号： G01R31/318572 ,  G11C5/063 ,  G11C11/417 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/11807 ,  H01L2924/0002 ,  H03K3/356008 ,  H03K3/35625 ,  H03K19/0016 ,  H01L2924/00

摘要： In a low power consumption mode in which prior data is retained upon power shutdown, the return speed thereof is increased. While use of an existent data retaining flip-flop may be considered, this is not preferred since it increases area overhead such as enlargement of the size of a cell. A power line for data retention for power shutdown is formed with wirings finer than a usual main power line. Preferably, power lines for a data retention circuit are considered as signal lines and wired by automatic placing and mounting. For this purpose, terminals for the power line for data retention are previously designed by providing the terminals therefor for the cell in the same manner as in the existent signal lines. Additional layout for power lines is no longer necessary for the cell, which enables a decrease in the area and design by an existent placing and routing tool.

摘要翻译： 在功率关闭时保留先前数据的低功耗模式下，其返回速度增加。 虽然可以考虑使用现有的数据保持触发器，但是这不是优选的，因为它增加了诸如扩大单元大小的面积开销。 用于电源关闭的数据保持的电源线由比通常的主电源线更细的布线形成。 优选地，用于数据保持电路的电力线被认为是信号线，并通过自动放置和安装进行布线。 为此，先前通过以与现有信号线相同的方式为小区提供终端来设计用于数据保持的电力线的终端。 电池线的附加布局不再需要，这使得现有的放置和布线工具能够减少面积和设计。

公开(公告)号：US20060146635A1

公开(公告)日：2006-07-06

申请号：US11363060

申请日：2006-02-28

申请人： Takao Watanabe ,  Kunio Uchiyama ,  Osamu Nishii ,  Naohiko Irie ,  Hiroyuki Mizuno

发明人： Takao Watanabe ,  Kunio Uchiyama ,  Osamu Nishii ,  Naohiko Irie ,  Hiroyuki Mizuno

IPC分类号： G11C5/14

CPC分类号： G06F1/3203 ,  G06F1/3287 ,  G11C5/147 ,  G11C11/417 ,  Y02D10/171

摘要： When a leakage current of a circuit block under a non-use state is reduced by means of a power switch, frequent ON/OFF operations of the switch within a short time invite an increase of consumed power, on the contrary. Because a pre-heating time is necessary from turn-on of the switch till the circuit block becomes usable, control of the switch during an operation deteriorates a processing time of a semiconductor device. The switch is ON/OFF-controlled with a task duration time of a CPU core for controlling logic circuits and memory cores as a unit. After the switch is turned off, the switch is again turned on before termination of the task in consideration of the pre-heating time.

公开(公告)号：US08122233B2

公开(公告)日：2012-02-21

申请号：US12124232

申请日：2008-05-21

申请人： Motokazu Ozawa ,  Naohiko Irie ,  Saneaki Tamaki ,  Hisayoshi Ide ,  Miki Hayakawa

发明人： Motokazu Ozawa ,  Naohiko Irie ,  Saneaki Tamaki ,  Hisayoshi Ide ,  Miki Hayakawa

IPC分类号： G06F9/00 ,  G06F15/177

CPC分类号： G06F1/3203 ,  G06F1/3243 ,  G06F1/3287 ,  Y02D10/152 ,  Y02D10/171 ,  Y02D50/20

摘要： An information processing device, including: a processing unit; a peripheral circuit module; and a boot address register, wherein the information processing device comprises a first operation mode and a second operation mode having an operating current which is lower than that of said first operation mode, wherein the boot address register holds an address of an instruction to be executed by said processing unit first when the boot address register returns from said second operation mode to said first operation mode, wherein the address is output from said boot address to the processing unit when said information processing device shifts from said second operation mode to said first operation mode.

摘要翻译： 一种信息处理装置，包括：处理单元; 外围电路模块; 以及引导地址寄存器，其中所述信息处理设备包括具有低于所述第一操作模式的操作电流的第一操作模式和第二操作模式，其中所述引导地址寄存器保存要执行的指令的地址 所述处理单元首先当所述引导地址寄存器从所述第二操作模式返回到所述第一操作模式时，其中当所述信息处理设备从所述第二操作模式转换到所述第一操作时，所述地址从所述引导地址输出到所述处理单元 模式。