公开(公告)号：US07124283B2

公开(公告)日：2006-10-17

申请号：US10457409

申请日：2003-06-10

申请人： Tetsuya Yamada ,  Naohiko Irie ,  Takanobu Tsunoda ,  Takahiro Irita ,  Keisuke Toyama ,  Masayuki Kabasawa

发明人： Tetsuya Yamada ,  Naohiko Irie ,  Takanobu Tsunoda ,  Takahiro Irita ,  Keisuke Toyama ,  Masayuki Kabasawa

IPC分类号： G06F5/00

CPC分类号： G06F9/3879 ,  G06F9/30174 ,  G06F9/4552

摘要： The present invention provides a hardware accelerator, which allows faster switching between processing modes. In an information processing device with a bytecode accelerator BCA for translating a stack-based intermediate code (bytecode) into register-based instructions, a selector SEL for switching between BCA and soft VM is posed between an instruction part FET and a decode part DEC and data transfer paths P4 and P5 are formed between BCA and the register file REG_FILE. When bytecode accelerator BCA is activated, the P3 side is selected by the selector SEL and the translated CPU instructions are transferred to the decode part DEC. If the intermediate language code cannot be translated by the BCA, the processing mode is switched to software processing. During switching between the modes, internal information of BCA can be transferred between BCA and REG_FILE in parallel, achieving faster mode switching.

摘要翻译： 本发明提供一种硬件加速器，其允许在处理模式之间更快地切换。 在具有用于将基于堆栈的中间码（字节码）转换为基于寄存器的指令的字节码加速器BCA的信息处理装置中，在指令部分FET和解码部分DEC之间存在用于在BCA和软VM之间切换的选择器SEL， 在BCA和寄存器文件REG_FILE之间形成数据传送路径P 4和P 5。 当字节码加速器BCA被激活时，选择器SEL选择P 3侧，转换的CPU指令被传送到解码部分DEC。 如果BCA不能翻译中间语言代码，则将处理模式切换到软件处理。 在模式切换期间，BCA的内部信息可以在BCA和REG_FILE之间并行传输，实现更快的模式切换。

公开(公告)号：US07493479B2

公开(公告)日：2009-02-17

申请号：US10458289

申请日：2003-06-11

申请人： Masayuki Kabasawa ,  Naohiko Irie ,  Takahiro Irita ,  Tetsuya Yamada ,  Takanobu Tsunoda

发明人： Masayuki Kabasawa ,  Naohiko Irie ,  Takahiro Irita ,  Tetsuya Yamada ,  Takanobu Tsunoda

IPC分类号： G06F9/30 ,  G06F9/40 ,  G06F15/00 ,  G06F7/38

CPC分类号： G06F9/30174 ,  G06F9/3851

摘要： A method and apparatus are provided for event detection for a multiple instruction-set processor. In one example of the apparatus, a data processing device comprises an instruction execution device configured to execute a first instruction set as specific instructions; an instruction conversion circuit configured to convert instructions of a second instruction set into a first instruction string of the first instruction set, and further configured to supply the first instruction string to the instruction execution device; and a counter device configured to count a prescribed event, wherein the instruction conversion circuit is further configured to output a prescribed instruction when the counter device is satisfied by a prescribed condition.

摘要翻译： 提供了一种用于多指令集处理器的事件检测的方法和装置。 在该装置的一个示例中，数据处理装置包括被配置为执行第一指令集作为特定指令的指令执行装置; 指令转换电路，被配置为将第二指令集的指令转换为第一指令集的第一指令串，并且还被配置为将第一指令串提供给指令执行装置; 以及计数器装置，被配置为对规定的事件进行计数，其中所述指令转换电路还被配置为当所述计数器装置满足规定条件时输出规定的指令。

公开(公告)号：US07178046B2

公开(公告)日：2007-02-13

申请号：US11095685

申请日：2005-04-01

申请人： Tetsuya Yamada ,  Tomoichi Hayashi ,  Sadaki Nakano ,  Takanobu Tsunoda ,  Osamu Nishii

发明人： Tetsuya Yamada ,  Tomoichi Hayashi ,  Sadaki Nakano ,  Takanobu Tsunoda ,  Osamu Nishii

IPC分类号： G06F1/32 ,  G06F9/30

CPC分类号： G06F9/3836 ,  G06F1/3203 ,  G06F1/3237 ,  G06F1/3243 ,  G06F1/3287 ,  G06F8/4432 ,  G06F9/30083 ,  G06F9/30145 ,  G06F9/30156 ,  G06F9/3017 ,  G06F9/3877 ,  G06F9/3885 ,  Y02D10/128 ,  Y02D10/152 ,  Y02D10/171 ,  Y02D10/41

摘要： A microprocessor includes a first cache memory, a first instruction fetch unit, a first instruction decoder, a first processing unit and a first latch that holds a control signal outputted from the first instruction decoder. When the first instruction fetch unit receives a first instruction performed by the first processing unit it outputs the first instruction to the first instruction decoder. When the first instruction fetch unit receives a second instruction which is not performed by the first processing unit, it outputs a specific instruction to the first instruction decoder, after which the supply of clock pulses to other latch circuits In the first processing unit is halted based on the control signal.

摘要翻译： 微处理器包括第一高速缓冲存储器，第一指令提取单元，第一指令解码器，第一处理单元和保存从第一指令译码器输出的控制信号的第一锁存器。 当第一指令提取单元接收到由第一处理单元执行的第一指令时，它向第一指令解码器输出第一指令。 当第一指令提取单元接收到不由第一处理单元执行的第二指令时，它向第一指令解码器输出特定指令，之后向其他锁存电路提供时钟脉冲在第一处理单元中基于暂停 对控制信号。

公开(公告)号：US20050169086A1

公开(公告)日：2005-08-04

申请号：US11095685

申请日：2005-04-01

申请人： Tetsuya Yamada ,  Tomoichi Hayashi ,  Sadaki Nakano ,  Takanobu Tsunoda ,  Osamu Nishii

发明人： Tetsuya Yamada ,  Tomoichi Hayashi ,  Sadaki Nakano ,  Takanobu Tsunoda ,  Osamu Nishii

IPC分类号： G06F9/38 ,  G06F1/32 ,  G06F7/00 ,  G06F9/318 ,  G06F9/45 ,  G11C7/00

CPC分类号： G06F9/3836 ,  G06F1/3203 ,  G06F1/3237 ,  G06F1/3243 ,  G06F1/3287 ,  G06F8/4432 ,  G06F9/30083 ,  G06F9/30145 ,  G06F9/30156 ,  G06F9/3017 ,  G06F9/3877 ,  G06F9/3885 ,  Y02D10/128 ,  Y02D10/152 ,  Y02D10/171 ,  Y02D10/41

摘要： A microprocessor including a first cache memory, a first instruction fetch unit coupled to the first cache memory, a first instruction decoder coupled to the first instruction fetch unit, and a first processing unit coupled to the first instruction decoder, wherein, when the first instruction fetch unit is inputted with a first instruction which is performed by the first processing unit, the first instruction fetch unit outputs the first instruction to the first instruction decoder, wherein when the first instruction fetch unit is inputted with a second instruction which is not performed by the first processing unit, the first instruction fetch unit outputs a specific instruction to the first instruction decoder, and wherein, in the case where the first instruction fetch unit outputs the specific instruction to the first instruction decoder, the supply of clock pulse to the first processing unit is halted.

摘要翻译： 包括第一高速缓冲存储器，耦合到第一高速缓存存储器的第一指令提取单元，耦合到第一指令提取单元的第一指令解码器和耦合到第一指令解码器的第一处理单元的微处理器，其中当第一指令 输入第一指令的第一指令由第一处理单元输入，第一指令提取单元向第一指令解码器输出第一指令，其中当第一指令提取单元输入第二指令时，第二指令不由第一指令执行， 第一处理单元，第一指令获取单元向第一指令解码器输出特定指令，并且其中，在第一指令提取单元向第一指令解码器输出特定指令的情况下，向第一指令解码器提供时钟脉冲 处理单元停止。

公开(公告)号：US06877087B1

公开(公告)日：2005-04-05

申请号：US09603965

申请日：2000-06-26

申请人： Tetsuya Yamada ,  Tomoichi Hayashi ,  Sadaki Nakano ,  Takanobu Tsunoda ,  Osamu Nishii

发明人： Tetsuya Yamada ,  Tomoichi Hayashi ,  Sadaki Nakano ,  Takanobu Tsunoda ,  Osamu Nishii

IPC分类号： G06F9/38 ,  G06F1/32 ,  G06F7/00 ,  G06F9/318 ,  G06F9/45

CPC分类号： G06F9/3836 ,  G06F1/3203 ,  G06F1/3237 ,  G06F1/3243 ,  G06F1/3287 ,  G06F8/4432 ,  G06F9/30083 ,  G06F9/30145 ,  G06F9/30156 ,  G06F9/3017 ,  G06F9/3877 ,  G06F9/3885 ,  Y02D10/128 ,  Y02D10/152 ,  Y02D10/171 ,  Y02D10/41

摘要： A microprocessor to reduce wasteful power consumption of the floating-point unit. An instruction invalidation logic circuit is utilized to substitute the instruction not-to-use-the-floating-point unit, in the instruction string supplied from the instruction cache, with an invalidating instruction, hold that invalidating instruction in the floating-point register, and supply that invalidating instruction to a floating-point decoder in the floating-point unit. In cases when the invalidating instruction was continuous, the power consumption in the floating-point data path as well as the in the floating-point decoder and floating-point register is reduced.

摘要翻译： 一种微处理器，用于减少浮点单元浪费的功耗。 使用指令无效化逻辑电路来代替从指令高速缓冲存储器提供的指令串中的不使用浮点单元的指令与无效指令，将该无效指令保持在浮点寄存器中， 并将该无效指令提供给浮点单元中的浮点解码器。 在无效指令连续的情况下，浮点数据路径以及浮点解码器和浮点寄存器的功耗降低。

公开(公告)号：US20070162529A1

公开(公告)日：2007-07-12

申请号：US11593542

申请日：2006-11-07

申请人： Makoto Sato ,  Takanobu Tsunoda ,  Masashi Takada

发明人： Makoto Sato ,  Takanobu Tsunoda ,  Masashi Takada

IPC分类号： G06J1/00

CPC分类号： G06F15/8007 ,  G06F15/7867

摘要： A dynamically reconfigurable processor having a wiring structure which enables flexible mapping of a program to the processor with a small wiring area is provided. The dynamically reconfigurable processor comprises: a first arithmetic circuit group composed of arithmetic circuits of a type Ai (i=1, 2, . . . , N); a second arithmetic circuit group composed of a part of an arithmetic circuit group included in the first arithmetic circuit group and an arithmetic circuit group of a type B which is connected thereto and different from the arithmetic circuit of the type Ai; inter-arithmetic-circuit wires mutually connecting the arithmetic circuits of the type Ai and the arithmetic circuits of the type B; and a switch group which causes the inter-arithmetic-circuit wires in the second arithmetic circuit group to be inter-arithmetic-circuit wires different from other inter-arithmetic-circuit wires and changes the connection order between the arithmetic circuits in the second arithmetic circuit group.

摘要翻译： 提供一种具有布线结构的动态可重构处理器，其能够以小布线区域灵活地将程序映射到处理器。 该动态可重构处理器包括：由类型Ai（i = 1,2，...，N）的运算电路组成的第一运算电路组; 由第一运算电路组中包括的算术电路组的一部分和与该类型的运算电路不同的类型B的运算电路组组成的第二运算电路组; 将类型Ai的运算电路和B型运算电路相互连接的运算间电路布线; 以及使第二运算电路组中的运算电路布线之间的运算电路布线与其他算术电路布线不同的开关组，并且改变第二运算电路中的运算电路之间的连接顺序 组。

公开(公告)号：US07571198B2

公开(公告)日：2009-08-04

申请号：US11593542

申请日：2006-11-07

申请人： Makoto Sato ,  Takanobu Tsunoda ,  Masashi Takada

发明人： Makoto Sato ,  Takanobu Tsunoda ,  Masashi Takada

IPC分类号： G06F7/38

CPC分类号： G06F15/8007 ,  G06F15/7867

摘要： A dynamically reconfigurable processor is provided having a wiring structure which enables flexible mapping of a program to the processor with a small wiring area. A first wire permits a first arrangement of circuit blocks and a second wire provided for changing the arrangement order of the circuit blocks. A switch is provided to switch between the first wire and the second wire. By virtue of this arrangement, a greater variety of calculations can be performed in the circuit without the necessity for increasing the number of operation blocks.

摘要翻译： 提供了具有布线结构的动态可重构处理器，其能够以小的布线区域灵活地将程序映射到处理器。 第一线允许电路块的第一布置和用于改变电路块的布置顺序的第二布线。 提供开关以在第一线和第二线之间切换。 通过这种布置，可以在电路中执行更多种类的计算，而不需要增加操作块的数量。

公开(公告)号：US20060190701A1

公开(公告)日：2006-08-24

申请号：US11271961

申请日：2005-11-14

申请人： Takanobu Tsunoda ,  Bryan Atwood ,  Masashi Takada ,  Hiroshi Tanaka

发明人： Takanobu Tsunoda ,  Bryan Atwood ,  Masashi Takada ,  Hiroshi Tanaka

IPC分类号： G06F15/00

CPC分类号： G06F15/16

摘要： There is provided at least one processor block including a plurality of load store interfaces (801, 804), a plurality of memory banks (821), an input/output port having at least one of an input port (850) and an output port (860), and a crossbar switch (810), and the crossbar switch connects the load store interface, the memory bank and the input/output port to each other and the load store interface constitutes a data processor in order to control a data transfer to the memory bank. Consequently, there is implemented a data processor having a high transfer throughput and a flexibility and efficiently treating stream data.

摘要翻译： 提供至少一个处理器块，其包括多个加载存储接口（801,804），多个存储体（821），具有输入端口（850）和输出端口（850）中的至少一个的输入/输出端口 （860）和交叉开关（810），并且交叉开关将负载存储接口，存储体和输入/输出端口彼此连接，并且负载存储接口构成数据处理器，以便控制数据传送 到记忆库。 因此，实现了具有高传输吞吐量和灵活性并且有效地处理流数据的数据处理器。

公开(公告)号：US06654305B2

公开(公告)日：2003-11-25

申请号：US10259777

申请日：2002-09-30

申请人： Takanobu Tsunoda ,  Osamu Nishii

发明人： Takanobu Tsunoda ,  Osamu Nishii

IPC分类号： G11C700

CPC分类号： G11C5/146

摘要： A system LSI including substrate-bias generation circuits for supplying substrate biases independent of each other to functional modules integrated in the system LSI, a substrate-bias control circuit for controlling the substrate-bias generation circuits and a substrate-bias control-value storage unit for storing control values to be supplied to the substrate-bias generation circuits. The control values stored in the substrate-bias control-value storage unit are set by carrying out a predetermined operation. As a result, it is possible to provide a device for implementing both a high-speed operation and low power consumption without lowering the yield and for finely controlling the power consumption during the operation.

摘要翻译： 一种系统LSI，包括用于将集成在系统LSI中的功能模块彼此独立地提供衬底偏压的衬底偏置生成电路，用于控制衬底偏置生成电路的衬底偏置控制电路和衬底偏置控制值存储单元 用于存储要提供给衬底偏置发生电路的控制值。 通过执行预定的操作来设定存储在基板偏置控制值存储单元中的控制值。 结果，可以提供一种用于实现高速操作和低功耗的装置，而不降低产量并精细地控制操作期间的功率消耗。

公开(公告)号：US06493255B2

公开(公告)日：2002-12-10

申请号：US10024008

申请日：2001-12-21

申请人： Osamu Nishii ,  Motonobu Tonomura ,  Takanobu Tsunoda

发明人： Osamu Nishii ,  Motonobu Tonomura ,  Takanobu Tsunoda

IPC分类号： G11C1100

CPC分类号： G11C15/04

摘要： A small-area associative memory for association by a value resulted from addition, with reduced carry delay, is provided. Adjacent 1-bit memory values and a signal depending on adjacent 2 bits of addition-inputs are inputted into a CAM memory cell constructed using MOS transistors, and a hit line is pulled down or pulled up in accordance with the input values.

摘要翻译： 提供了一个小面积的联想记忆，用于通过加法产生的值与减少的进位延迟相关联。 相邻的1位存储器值和取决于相邻2位的相加输入的信号被输入到使用MOS晶体管构成的CAM存储单元中，并且根据输入值将命中线拉下或上拉。