公开(公告)号：US20100065846A1

公开(公告)日：2010-03-18

申请号：US12092238

申请日：2005-11-02

申请人： Masayuki SATOH

发明人： Masayuki SATOH

IPC分类号： H01L23/544

CPC分类号： G01R31/2818 ,  G01R31/2884 ,  G01R31/318533 ,  G11C29/40 ,  G11C29/48 ,  G11C29/56 ,  G11C2029/0401 ,  G11C2029/3202 ,  G11C2029/5602 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/12044 ,  H01L2924/13091 ,  H01L2924/15192 ,  H01L2924/19105 ,  H01L2924/00 ,  H01L2224/0401

摘要： This invention relates to a system in package including a plurality of integrated circuit chips and a substrate on which the plurality of integrated circuit chips are mounted and characterized in that a testability circuit for facilitating a test on at least one of the integrated circuit chips is incorporated into the substrate. The testability circuit incorporated into the substrate is formed by embedding a so-called WLCSP integrated circuit chip into the substrate. Alternatively, the testability circuit is formed by using a transistor element formed by using a semiconductor layer formed on the substrate. By incorporating the testability circuit into the substrate as described above, it is possible to realize a system in package facilitated in test without increases in size and cost.

摘要翻译： 本发明涉及包括多个集成电路芯片的多个集成电路芯片和其上安装有多个集成电路芯片的基板的系统，其特征在于，包括用于促进至少一个集成电路芯片的测试的可测试性电路 进入基板。 通过将所谓的WLCSP集成电路芯片嵌入到基板中来形成结合到基板中的可测试性电路。 或者，通过使用通过使用形成在基板上的半导体层形成的晶体管元件来形成可测试性电路。 通过将可测试性电路并入到基板中，可以在不增加尺寸和成本的情况下实现测试中促进的封装体系。