公开(公告)号：US20100142418A1

公开(公告)日：2010-06-10

申请号：US12665079

申请日：2009-05-13

申请人： Shinichiro Nishioka ,  Keisuke Sakai ,  Masayuki Toyama ,  Tsutomu Sekibe

发明人： Shinichiro Nishioka ,  Keisuke Sakai ,  Masayuki Toyama ,  Tsutomu Sekibe

IPC分类号： H04B1/44

CPC分类号： H04L5/14 ,  H04L5/1438 ,  H04L5/16 ,  H04W72/1247

摘要： The object of the present invention is to provide a data communication system in which a communication scheme is switched without a decrease in communication efficiency.In a data communication system including first and second devices that are capable of performing full-duplex communication and half-duplex communication via a set of channels connecting the first and second devices, the first device transmits, via the set of channels, to the second device a first communication flag indicating whether half-duplex communication is to be specified in accordance with a communication processing capability of the first device, the second device transmits, via the set of channels, to the first device a second communication flag indicating whether half-duplex communication is to be specified in accordance with a communication processing capability of the second device, and the first and second devices select either a full-duplex communication scheme or a half-duplex communication scheme depending on the first and second communication flags in compliance with a procedure predetermined between the devices and perform data communication in the selected communication scheme, the selected communication scheme conforming to the communication processing capability of each device.

摘要翻译： 本发明的目的是提供一种在不降低通信效率的情况下切换通信方案的数据通信系统。 在包括能够经由连接第一和第二设备的一组通道执行全双工通信和半双工通信的第一和第二设备的数据通信系统中，第一设备经由一组信道发送到第二设备 设备指示是否根据第一设备的通信处理能力指定半双工通信的第一通信标志，第二设备经由该组信道向第一设备发送第二通信标志， 双向通信将根据第二设备的通信处理能力来指定，并且第一和第二设备根据第一和第二通信标志选择全双工通信方案或半双工通信方案，其符合 在所述设备之间预定的过程，并在所选择的通信中进行数据通信 离子方案，所选择的通信方案符合每个设备的通信处理能力。

公开(公告)号：US06938144B2

公开(公告)日：2005-08-30

申请号：US10101268

申请日：2002-03-20

申请人： Masayuki Toyama ,  Tsutomu Sekibe

发明人： Masayuki Toyama ,  Tsutomu Sekibe

IPC分类号： G06F12/00 ,  G06F12/02 ,  G06F12/16 ,  G06F12/10

CPC分类号： G06F12/0246 ,  G06F12/0292 ,  G06F2212/2022 ,  G06F2212/7201

摘要： A memory device with a nonvolatile memory and RAM for accessing the nonvolatile memory is generally provided with a table to convert a logical address to a physical address, however, in the invention, the table is divided to a first table on RAM and a second table on the nonvolatile memory. The first table converts specific bits of the logical address to a first physical address indicating a location of the second table. The second table converts the other bits of the logical address to a physical address of a representative page of pages contained in a storage area corresponding to the logical address. A unit operable to access data (a writing unit operable to, a reading unit operable to, and an erasing unit operable to) reaches a target physical address based on the logical address. Such configuration can reduce the capacity of each conversion table.

摘要翻译： 具有用于访问非易失性存储器的非易失性存储器和RAM的存储器件通常设置有用于将逻辑地址转换为物理地址的表，然而，在本发明中，该表被划分为RAM上的第一表和第二表 在非易失性存储器上。 第一表将逻辑地址的特定比特转换成指示第二表的位置的第一物理地址。 第二表将逻辑地址的其他位转换为与逻辑地址对应的存储区域中包含的页面的代表页的物理地址。 可操作以访问数据的单元（可操作的读取单元，可操作的读取单元和可擦除单元）可以基于逻辑地址到达目标物理地址。 这样的配置可以减少每个转换表的容量。

公开(公告)号：US06680870B2

公开(公告)日：2004-01-20

申请号：US10351339

申请日：2003-01-27

申请人： Masayuki Toyama ,  Tsutomu Sekibe

发明人： Masayuki Toyama ,  Tsutomu Sekibe

IPC分类号： G11C1604

CPC分类号： G06F11/1064

摘要： A memory device that is free from problems resulted from the characteristics of nonvolatile memory chips. The problems are specifically those occurring at the time of data transfer between nonvolatile memory chips, e.g., data error or program error occurring after data transfer. In the memory device, an error correction code process unit applies error detection to data read from a nonvolatile memory chip to a data line for data transfer. For such detection, an error correction code for the data is referred to. At the time of data transfer between the nonvolatile memory chips, if the data is detected as containing a correctable error, a writing unit writes the corrected data to a nonvolatile memory, which is the transfer destination. In this manner, at the time of data transfer between the nonvolatile memory chips, the error never fails to be detected before data writing.

摘要翻译： 不存在因非易失性存储器芯片的特性导致的问题的存储器件。 这些问题特别是在非易失性存储器芯片之间的数据传输时发生的问题，例如在数据传输之后发生的数据错误或程序错误。 在存储装置中，错误校正码处理单元对从非易失性存储器芯片读取到数据线的数据进行误差检测。 对于这种检测，参考数据的纠错码。 在非易失性存储器芯片之间的数据传输时，如果数据被检测为包含可校正的错误，则写入单元将校正的数据写入作为转移目的地的非易失性存储器。 以这种方式，在非易失性存储器芯片之间的数据传送时，在数据写入之前不会检测出错误。

公开(公告)号：USRE42263E1

公开(公告)日：2011-03-29

申请号：US11896278

申请日：2007-08-30

申请人： Masayuki Toyama ,  Tsutomu Sekibe

发明人： Masayuki Toyama ,  Tsutomu Sekibe

IPC分类号： G06F12/00

CPC分类号： G06F12/0246 ,  G06F12/0292 ,  G06F2212/2022 ,  G06F2212/7201

摘要： A memory device with a nonvolatile memory and RAM for accessing the nonvolatile memory is generally provided with a table to convert a logical address to a physical address, however, in the invention, the table is divided to a first table on RAM and a second table on the nonvolatile memory. The first table converts specific bits of the logical address to a first physical address indicating a location of the second table. The second table converts the other bits of the logical address to a physical address of a representative page of pages contained in a storage area corresponding to the logical address. A unit operable to access data (a writing unit operable to, a reading unit operable to, and an erasing unit operable to) reaches a target physical address based on the logical address. Such configuration can reduce the capacity of each conversion table.

摘要翻译： 具有用于访问非易失性存储器的非易失性存储器和RAM的存储器件通常设置有用于将逻辑地址转换为物理地址的表，然而，在本发明中，该表被划分为RAM上的第一表和第二表 在非易失性存储器上。 第一表将逻辑地址的特定比特转换成指示第二表的位置的第一物理地址。 第二表将逻辑地址的其他位转换为与逻辑地址对应的存储区域中包含的页面的代表页的物理地址。 可操作以访问数据的单元（可操作的读取单元，可操作的读取单元和可擦除单元）可以基于逻辑地址到达目标物理地址。 这样的配置可以减少每个转换表的容量。

公开(公告)号：US08693379B2

公开(公告)日：2014-04-08

申请号：US12676433

申请日：2009-07-21

申请人： Shinichiro Nishioka ,  Tsutomu Sekibe

发明人： Shinichiro Nishioka ,  Tsutomu Sekibe

IPC分类号： H04L5/16

CPC分类号： H04L5/14 ,  H04L5/16

摘要： A communication system performs communication while switching between full-duplex communication and half-duplex communication. A slave device, which receives command packet signals requesting to write or read data from the master device, stores information in a response packet signal that specifies half-duplex communication in response to one of the received packet signals, and transmits the response packet signal to the master device, when the number of the received command packet signals has reached the maximum number of the command packet signals storable in a command signal queue.

摘要翻译： 通信系统在全双工通信和半双工通信之间切换时进行通信。 接收请求从主设备写入或读取数据的命令分组信号的从设备响应于所接收的分组信号之一将信息存储在指定半双工通信的响应分组信号中，并将响应分组信号发送到 当接收到的命令分组信号的数量已经达到可存储在命令信号队列中的命令分组信号的最大数量时，主设备。

公开(公告)号：US08351356B2

公开(公告)日：2013-01-08

申请号：US12674045

申请日：2009-06-11

申请人： Shinichiro Nishioka ,  Hiroshi Suenaga ,  Tsutomu Sekibe ,  Isao Kato ,  Tadashi Ono ,  Hideyuki Yamada

发明人： Shinichiro Nishioka ,  Hiroshi Suenaga ,  Tsutomu Sekibe ,  Isao Kato ,  Tadashi Ono ,  Hideyuki Yamada

IPC分类号： H04L5/16 ,  H04L5/14 ,  G06F13/12

CPC分类号： H04L25/0272 ,  H04L5/14 ,  H04L5/1438 ,  H04L5/16

摘要： A data communication system for starting transmission and reception of target data for processing upon recognition that switching between communication modes is completed. The data communication system includes a master communication device and a slave communication device that continuously perform, at a time of switching from half-duplex communication to full-duplex communication, (i) a handshake using a directional control code indicating the switching and a preamble code indicating completion of the switching and (ii) a handshake using the preamble code and an acknowledge code indicating receipt of the preamble code, whereby each of the devices recognizes that the switching between communication modes by the opposite device is completed and starts transmission and reception of the target data.

摘要翻译： 一种数据通信系统，用于在识别出完成通信模式之间的切换的情况下开始用于处理的目标数据的发送和接收。 数据通信系统包括在从半双工通信切换到全双工通信时连续执行主通信设备和从通信设备，（i）使用指示切换的方向控制代码的握手和前导码 指示切换完成的代码和（ii）使用前导码的握手和指示接收前导码的确认代码，由此每个设备识别出相对设备的通信模式之间的切换完成并开始发送和接收 的目标数据。

公开(公告)号：US20110182216A1

公开(公告)日：2011-07-28

申请号：US12995558

申请日：2009-05-29

申请人： Tadashi Ono ,  Isao Kato ,  Hideyuki Yamada ,  Shinichiro Nishioka ,  Hiroshi Suenaga ,  Tsutomu Sekibe

发明人： Tadashi Ono ,  Isao Kato ,  Hideyuki Yamada ,  Shinichiro Nishioka ,  Hiroshi Suenaga ,  Tsutomu Sekibe

IPC分类号： H04B1/44

CPC分类号： H04L5/16 ,  H04L5/18 ,  H04L25/14

摘要： An interrupt request cannot be transmitted while a data read command or a data write command transmitted from a host device to a slave device is being processed in a half-duplex mode. Disclosed are a host device and a slave device that are set to a full-duplex mode by temporarily switching the communication direction of a first transmission channel or a second transmission channel after completing transmission and reception of a predetermined number of data packets in the half-duplex mode. The host device or the slave device can thus transmit an interrupt request, such as a request associated with a wait status or a busy status, to its communication target using the temporary full-duplex mode. This enables the host device or the slave device to process such an interrupt request during high-speed data transfer performed in the half-duplex mode.

摘要翻译： 当从主机设备发送到从设备的数据读取命令或数据写入命令正在以半双工模式进行处理时，不能发送中断请求。 公开了一种主机设备和从设备，其通过在完成在半双工模式下的预定数量的数据分组的传输和接收之后临时切换第一传输信道或第二传输信道的通信方向而被设置为全双工模式， 双工模式。 因此主机设备或从设备可以使用临时全双工模式向其通信目标传送诸如与等待状态或忙状态相关联的请求的中断请求。 这使得主机设备或从设备在半双工模式下执行的高速数据传输期间处理这样的中断请求。

公开(公告)号：US06633926B1

公开(公告)日：2003-10-14

申请号：US09450873

申请日：1999-11-29

申请人： Masaaki Harada ,  Tsutomu Sekibe

发明人： Masaaki Harada ,  Tsutomu Sekibe

IPC分类号： G06F1300

CPC分类号： G06F13/28

摘要： A DMA transfer device transfers data from a first region to a second region in a memory allowing high-speed page access. The DMA transfer device includes: a first detecting unit for detecting a plurality of read areas that form the first region, each read area being located between page boundaries; a second detecting unit for detecting a plurality of write areas that form the second region, each write area being located between page boundaries; and an access unit for performing high-speed page access to each of the read areas and each of the write areas.

摘要翻译： DMA传输设备将数据从第一区域传送到允许高速页面访问的存储器中的第二区域。 DMA传送装置包括：第一检测单元，用于检测形成第一区域的多个读取区域，每个读取区域位于页面边界之间; 第二检测单元，用于检测形成第二区域的多个写入区域，每个写入区域位于页面边界之间; 以及用于对每个读取区域和每个写入区域执行高速页面访问的访问单元。

公开(公告)号：US07793083B2

公开(公告)日：2010-09-07

申请号：US11667762

申请日：2005-11-24

申请人： Masaaki Harada ,  Tsutomu Sekibe

发明人： Masaaki Harada ,  Tsutomu Sekibe

IPC分类号： G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F15/00

CPC分类号： G06F12/0891 ,  G06F12/14 ,  G06F12/1491 ,  G06F21/10 ,  G06F21/105 ,  G06F21/6227 ,  G06F21/79 ,  G06F21/85 ,  G06F2221/2105 ,  G06F2221/2137

摘要： A processor (10) manages, in an instruction management unit (103) and a data attribute management unit (105), secure attributes indicating whether instruction code and data stored in an instruction cache (102) and a data cache (104) of the processor (10) are confidential information. When the instruction code and the data are confidential information, the processor (10) also manages secure processing identification information for indicating in which secure process the confidential information is to be used. When the operating mode is switched from the secure mode to the normal mode, only the confidential information is disabled by a memory disabling unit (108). This prevents confidential information from being analyzed by the processor in the normal mode.

摘要翻译： 处理器（10）在指令管理单元（103）和数据属性管理单元（105）中管理指示存储在指令高速缓存（102）和数据高速缓存（104）中的指令代码和数据的安全属性 处理器（10）是机密信息。 当指令代码和数据是机密信息时，处理器（10）还管理安全处理识别信息，用于指示在哪个安全处理中使用机密信息。 当操作模式从安全模式切换到正常模式时，只有秘密信息被存储器禁用单元（108）禁用。 这防止在正常模式下由处理器分析机密信息。

公开(公告)号：US07529938B2

公开(公告)日：2009-05-05

申请号：US09936157

申请日：2001-01-12

申请人： Osamu Shibata ,  Taihei Yugawa ,  Tsutomu Sekibe ,  Teruto Hirota ,  Yoshiyuki Saito ,  Toshihiko Otake

发明人： Osamu Shibata ,  Taihei Yugawa ,  Tsutomu Sekibe ,  Teruto Hirota ,  Yoshiyuki Saito ,  Toshihiko Otake

IPC分类号： H04L9/00 ,  G06F12/14 ,  G06F17/30 ,  H04N7/167 ,  H04K1/00

CPC分类号： G06F21/445 ,  G06F2221/2129 ,  Y10S707/99939

摘要： An authentication communication system includes an storage medium having an area for storing digital information and an access device for reading/writing digital information from/into the area. The access device authenticates whether the storage medium is authorized according to a challenge-response authentication protocol in which scrambled access information generated by scrambling the access information which shows the area is used. The storage medium authenticates whether the access device is authorized. When the access device and the storage medium have authenticated each other as authorized devices, the access device reads/writes digital information from/into the area in the storage medium according to the access information separated from the scrambled access information by the access device.

摘要翻译： 认证通信系统包括具有用于存储数字信息的区域的存储介质和用于从该区域读入/写入数字信息的访问设备。 访问设备根据询问 - 响应认证协议来认证存储介质是否被授权，其中使用通过对显示该区域的访问信息进行加扰而生成的加扰访问信息。 存储介质验证访问设备是否被授权。 当接入设备和存储介质彼此认证为授权设备时，接入设备根据由接入设备与加扰接入信息分离的接入信息，将/从数据信息读入/写入存储介质中的区域。