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11 条记录 (耗时 0.03 秒)

    Multipath noise reducer, audio output circuit, and FM receiver
    1.
    发明授权
    Multipath noise reducer, audio output circuit, and FM receiver 失效
    多路径减噪器，音频输出电路和FM接收器

    公开(公告)号：US06725027B1

    公开(公告)日：2004-04-20

    申请号：US09624009

    申请日：2000-07-21

    申请人： Masayuki Tsuji ,  Eiji Asano ,  Masahiro Tsujishita ,  Kenichi Taura ,  Masayuki Ishida

    发明人： Masayuki Tsuji ,  Eiji Asano ,  Masahiro Tsujishita ,  Kenichi Taura ,  Masayuki Ishida

    IPC分类号： H04B110

    CPC分类号： H04B1/1669 ,  H04B1/1081

    摘要： A multipath noise reducer detects and removes the individual noise spikes occurring in an interval of multipath noise, thereby reducing the multipath noise with minimal distortion of the audio output signal. The multipath noise spikes are detected by comparing a rectified signal with a threshold signal derived from the rectified signal. When the multipath noise reducer is used in an FM stereo radio receiver, stereo separation may also be controlled according to the detection of multipath noise.

    摘要翻译： 多径噪声减少器检测并去除在多径噪声间隔中出现的各个噪声尖峰，从而以最小的音频输出信号失真减少多路径噪声。 通过将整流信号与从整流信号导出的阈值信号进行比较来检测多径噪声尖峰。 当FM立体声无线电接收机中使用多路径降噪器时，也可以根据多路径噪声的检测来控制立体声分离。

    System with reduced instruction set processor accessing plural memories at different speeds using bank interleaving
    3.
    发明授权
    System with reduced instruction set processor accessing plural memories at different speeds using bank interleaving 失效
    具有精简指令集处理器的系统利用存储体交错以不同速度访问多个存储器

    公开(公告)号：US5386537A

    公开(公告)日：1995-01-31

    申请号：US766524

    申请日：1991-09-27

    申请人： Eiji Asano

    发明人： Eiji Asano

    IPC分类号： G06F9/38 ,  G06F15/78 ,  G06F13/00

    CPC分类号： G06F9/3814 ,  G06F15/7814 ,  G06F15/7857 ,  G06F9/3802 ,  G06F9/3824

    摘要： A data processor adopts a CPU that is represented by an RISC type CPU and capable of processing one instruction in one clock cycle. The data processor has an instruction bus and a data bus independently of each other and includes an EPROM connected to the instruction bus and a DRAM connected to the data bus. The RISC type CPU accesses the EPROM with no wait states and the DRAM with one wait state.

    摘要翻译： 数据处理器采用由RISC型CPU表示的CPU，能够在一个时钟周期内处理一个指令。 数据处理器具有彼此独立的指令总线和数据总线，并且包括连接到指令总线的EPROM和连接到数据总线的DRAM。 RISC型CPU访问没有等待状态的EPROM，DRAM等待一个等待状态。

    Ornamental tape or ribbon
    6.
    发明授权
    Ornamental tape or ribbon 失效
    装饰带或丝带

    公开(公告)号：US5545486A

    公开(公告)日：1996-08-13

    申请号：US359842

    申请日：1994-12-20

    申请人： Eiji Asano ,  Yoshiko Iwaki

    发明人： Eiji Asano ,  Yoshiko Iwaki

    IPC分类号： A41G1/00 ,  B44C5/00 ,  D04D7/10

    CPC分类号： D04D7/10

    摘要： An ornamental tape or ribbon having a base portion; a plurality of spindle-shaped tape portions extending from at least one side of the base portion; a plurality of suspended tape portions vertically extending from one of an upper and a lower side of the base portion; and a fastening tape portion vertically extending from another of an upper side and a lower side of the base portion across the base portion and having a tab for engagement in a slot where the vertically extending tape portions join the base portion.

    摘要翻译： 具有基部的装饰带或带; 从所述基部的至少一侧延伸的多个纺锤状带部; 从所述基部的上侧和下侧中的一个垂直延伸的多个悬挂带部分; 以及紧固带部分，其从基部的上侧和下侧的另一侧穿过基部垂直延伸，并且具有用于接合在垂直延伸的带部分接合基部的槽中的突片。

    Decoration for use on packages
    10.
    发明授权
    Decoration for use on packages 失效
    装饰用于包装

    公开(公告)号：US5116687A

    公开(公告)日：1992-05-26

    申请号：US527411

    申请日：1990-05-23

    申请人： Eiji Asano ,  Yoshiko Iwaki

    发明人： Eiji Asano ,  Yoshiko Iwaki

    IPC分类号： D04D7/04 ,  D04D7/10

    CPC分类号： D04D7/105 ,  D04D7/10

    摘要： An improvement in a decoration consisted of a belt shaped strip with plural segments longitudinally interconnected both edges of which segments are rounded out in substantially in symmetry and a looped elastic string folded and passed through plural holes provided on suitable positions of the belt shaped strip, the improvement comprising a decorative configuration provided on one end segment alone and consisted of at least two decorative pieces, said decorative configuration being formed only on one side of the segment with respect to the longitudinal axis of the belt-shaped strip.

    摘要翻译： 装饰的改进包括带状条带，其带有多个纵向相互连接的部分，两条边缘的边缘基本上对称地被圆化，并且环形的弹性绳折叠并穿过设置在带状条带的合适位置上的多个孔， 改进包括仅在一个端部部分上设置并由至少两个装饰件组成的装饰构造，所述装饰构造仅在片段的一侧相对于带状条的纵向轴线形成。