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公开(公告)号：US5081607A
公开(公告)日：1992-01-14
申请号：US483859
申请日：1990-02-23
CPC分类号： G06F7/505 , G06F9/30036 , G06F2207/3816 , G06F2207/3828
摘要： A digital arithmetic logic unit in which the carry chain is subdivided into a series of bit fields allowing independent and simultaneous data manipulation to be undertaken in each of the bit fields. Division of the carry chain is achieved via a carry chain selector consisting of a series of multiplexers, one being placed between each pair of adjacent stages of the carry chain. Each multiplexer has two data inputs, one of which forms the carry to the next stage of the carry chain. The carry selected either continues the computation or defines the end of one bit field and provides the least significant carry-in bit to the next bit field. This selection of the carry by the multiplexer is under control of a programmable register, thus allowing variable division of the carry chain.
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公开(公告)号：US5210723A
公开(公告)日：1993-05-11
申请号：US606262
申请日：1990-10-31
CPC分类号： G11C8/12 , G11C7/1015 , G11C7/1021
摘要： In a memory addressable by row and by column and operable in page mode whereby multiple column cycles are performed within a single row cycle, an arrangement is provided for stepping the row address for selected column cycles whereby sustained page mode operation can be provided throughout memory address space. Preferably, stepping occurs in response to a row change signal supplied when a column address strobe becomes active and the direction of stepping is determined by a mode signal supplied when a row address strobe becomes active. Memory segmentation is employed to facilitate simultaneous activation and restoring of multiple rows.
摘要翻译： 在可通过行和列寻址并且以页面模式操作的存储器中，在单个行周期内执行多个列周期，提供了用于对所选列周期的行地址进行步进的布置，从而可以在存储器地址中提供持续的页面模式操作 空间。 优选地，当列地址选通变为有效时响应于提供的行改变信号而发生步进，并且当行地址选通变为有效时由提供的模式信号确定步进方向。 采用内存分段来促进多行的同时激活和恢复。
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公开(公告)号：US5280616A
公开(公告)日：1994-01-18
申请号：US890330
申请日：1992-05-26
申请人： Nicholas D. Butler , Malcolm D. Buttimer , Brian C. Homewood , Steven P. Larky , Roderick M. West , Paolo G. Sidoli
发明人： Nicholas D. Butler , Malcolm D. Buttimer , Brian C. Homewood , Steven P. Larky , Roderick M. West , Paolo G. Sidoli
CPC分类号： G06F9/4881 , G06F9/30043 , G06F9/30141 , G06F9/3851 , G06F9/3861 , G06F9/461 , G06F11/14
摘要： In a logic circuit having clocked state latches and combinatorial logic for functional processing of a task in response to functional clocking of the state latches, the state latches are additionally interconnected to form a scannable chain of latches, and task switching logic is provided for suspending task processing by interrupting the functional clocking of the state latches and, during such suspension, scanning the state latches such that existing contents of the state latches defining a task state can be saved from the state latches or new contents defining a task state can be loaded into the state latches. The invention provides an efficient means for switching tasks being performed by a logic circuit in a multiprocessing enviornment.
摘要翻译： 在具有时钟状态锁存器和组合逻辑的逻辑电路中，响应于状态锁存器的功能时钟来执行任务的功能处理，状态锁存器被附加地互连以形成可扫描的锁存器链，并且提供任务切换逻辑用于暂停任务 通过中断状态锁存器的功能时钟来处理，并且在这种暂停期间扫描状态锁存器，使得可以从状态锁存器或定义任务状态的新内容中保存定义任务状态的状态锁存器的现有内容， 状态锁定。 本发明提供了一种用于在多处理环境中由逻辑电路执行的切换任务的有效手段。
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4.发明授权Step waveform generator and CRT vertical timebase incorporating such a generator 失效步进波形发生器和CRT垂直时基，并入这样一台发电机
公开(公告)号：US4549118A
公开(公告)日：1985-10-22
申请号：US595127
申请日：1984-03-30
申请人： Terence G. Cole , Roderick M. West
发明人： Terence G. Cole , Roderick M. West
摘要： A step waveform generator includes a cup and bucket circuit in which charging and discharging a cup capacitor (C1) with predetermined units of charge is achieved, in response to a train of pulses supplied to its input terminal (1), by means of an operational amplifier (2) continuously monitoring the voltage across the cup capacitor and alternately supplying charging current and discharging current from a first and second constant current source (I1 and I2) respectively via separate feedback loops (T3, T2 and T4, T7, T6) of the amplifier. The constant currents, or multiples or sub-multiples of the constant currents, providing each individual unit of charge, are generated by current mirrors (T8, T9, T10) and added sequentially to a bucket capacitor C2. The size of each individual step of the resultant voltage waveform derived from the bucket capacitor and appearing at output terminal 4 depends upon the combination of mirrored increments of current selected by switch (S1, S2) and added to the bucket capacitor. The waveform generator is particularly useful when driven by CRT horizontal sync pulses to provide a vertical timebase circuit generating a stepped voltage waveform instead of the more customary ramp voltage waveform. Appropriate combination of the outputs of the mirrors by judicious operation of the switches S1, S2 controls field interlace and single and multiple line skips.
摘要翻译： 一种步进波形发生器，包括一个杯形和斗式电路，其中响应于提供给其输入端子（1）的脉冲序列，通过一个操作的方式实现了以预定的充电单元对杯形电容器（C1）进行充电和放电 放大器（2）连续监测杯电容器两端的电压，并分别通过分别的反馈回路（T3，T2和T4，T7，T6）分别从第一和第二恒流源（I1和I2）提供充电电流和放电电流 放大器。 通过电流镜（T8，T9，T10）产生提供每个单独电荷的恒定电流的恒定电流或倍数或次倍数，并依次添加到桶式电容器C2。 从铲斗电容器导出并出现在输出端子4处的合成电压波形的每个单独步长的大小取决于由开关（S1，S2）选择的相加的电流的镜像增量的组合，并加到铲斗电容器上。 当由CRT水平同步脉冲驱动时，波形发生器特别有用，以提供垂直时基电路，而不是采用更常用的斜坡电压波形。 通过开关S1，S2的明智操作，反射镜的输出的适当组合控制场交错和单行和多行跳线。
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