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公开(公告)号：US20080167853A1
公开(公告)日：2008-07-10
申请号：US11621361
申请日：2007-01-09
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G01R31/31704 , G01R31/318357 , G06F11/261
摘要： A general purpose computational resource is provided for performing general purpose operations of a system. A special purpose computational resource is coupled to the general purpose computational resource. The special purpose computational resource is provided for: storing test patterns, a description of integrated circuitry, and a description of hardware for testing the integrated circuitry; and executing software for simulating an operation of the described hardware's testing of the described integrated circuitry in response to the test patterns
摘要翻译： 提供通用计算资源用于执行系统的通用操作。 专用计算资源与通用计算资源相连。 专用计算资源用于：存储测试模式，集成电路的描述以及用于测试集成电路的硬件描述; 以及执行用于模拟所述硬件对所述集成电路的测试的响应于所述测试模式的软件
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公开(公告)号：US20080288230A1
公开(公告)日：2008-11-20
申请号：US12130675
申请日：2008-05-30
IPC分类号： G06F17/50
CPC分类号： G01R31/31704 , G01R31/318357 , G06F17/5022
摘要： A design structure is embodied in a machine readable medium for designing, manufacturing, or testing integrated circuitry. The design structure includes a general purpose computational resource for performing general purpose operations of a system. A special purpose computational resource is coupled to the general purpose computational resource. The special purpose computational resource is for: storing test patterns, a description of the integrated circuitry, and a description of hardware for testing the integrated circuitry; and executing software for simulating an operation of the described hardware's testing of the described integrated circuitry in response to the test patterns.
摘要翻译： 设计结构体现在用于设计，制造或测试集成电路的机器可读介质中。 该设计结构包括用于执行系统的通用操作的通用计算资源。 专用计算资源与通用计算资源相连。 专用计算资源用于：存储测试模式，集成电路的描述以及用于测试集成电路的硬件描述; 以及执行用于模拟所述硬件对所述集成电路的测试的响应于所述测试模式的软件。
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公开(公告)号：US08027825B2
公开(公告)日：2011-09-27
申请号：US12130675
申请日：2008-05-30
CPC分类号： G01R31/31704 , G01R31/318357 , G06F17/5022
摘要： A design structure is embodied in a machine readable medium for designing, manufacturing, or testing integrated circuitry. The design structure includes a general purpose computational resource for performing general purpose operations of a system. A special purpose computational resource is coupled to the general purpose computational resource. The special purpose computational resource is for: storing test patterns, a description of the integrated circuitry, and a description of hardware for testing the integrated circuitry; and executing software for simulating an operation of the described hardware's testing of the described integrated circuitry in response to the test patterns.
摘要翻译： 设计结构体现在用于设计，制造或测试集成电路的机器可读介质中。 该设计结构包括用于执行系统的通用操作的通用计算资源。 专用计算资源与通用计算资源相连。 专用计算资源用于：存储测试模式，集成电路的描述以及用于测试集成电路的硬件描述; 以及执行用于模拟所述硬件对所述集成电路的测试的响应于所述测试模式的软件。
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公开(公告)号：US08006155B2
公开(公告)日：2011-08-23
申请号：US11621361
申请日：2007-01-09
IPC分类号： G01R31/28
CPC分类号： G06F17/5022 , G01R31/31704 , G01R31/318357 , G06F11/261
摘要： A general purpose computational resource is provided for performing general purpose operations of a system. A special purpose computational resource is coupled to the general purpose computational resource. The special purpose computational resource is provided for: storing test patterns, a description of integrated circuitry, and a description of hardware for testing the integrated circuitry; and executing software for simulating an operation of the described hardware's testing of the described integrated circuitry in response to the test patterns.
摘要翻译： 提供通用计算资源用于执行系统的通用操作。 专用计算资源与通用计算资源相连。 专用计算资源用于：存储测试模式，集成电路的描述以及用于测试集成电路的硬件描述; 以及执行用于模拟所述硬件对所述集成电路的测试的响应于所述测试模式的软件。
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5.发明授权公开(公告)号：US07900086B2
公开(公告)日：2011-03-01
申请号：US12129030
申请日：2008-05-29
IPC分类号： G06F11/00
CPC分类号： G06F11/2236
摘要： A mechanism for accelerating test, debug and failure analysis of a multiprocessor device is provided. With the mechanism, on-chip trace logic is utilized to receive internal signals from logic provided in modules of the multiprocessor device. The modules are preferably copies of one another such that, given the same inputs, each module should operate in the same manner and generate the same output as long as the modules are operating properly. The modules are provided with the same inputs and the internal signals of the modules are traced using an on-chip trace bus and on-chip trace logic analyzer to perform the trace. The internal signals from one module are compared against another module so as to determine if there is any discrepancy which would indicate a fault. Additional pairs of modules may be compared to pinpoint a faulty module that is the source of the fault.
摘要翻译： 提供了一种用于加速多处理器设备的测试，调试和故障分析的机制。 利用该机制，利用片上跟踪逻辑来从多处理器设备的模块中提供的逻辑接收内部信号。 这些模块优选地是彼此的副本，使得在给定相同的输入的情况下，每个模块应该以相同的方式操作并产生相同的输出，只要模块正常运行即可。 模块提供相同的输入，并使用片上跟踪总线和片上跟踪逻辑分析仪跟踪模块的内部信号，以执行跟踪。 将来自一个模块的内部信号与另一个模块进行比较，以确定是否存在指示故障的差异。 可以对额外的模块对进行比较，以确定故障源的故障模块。
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6.发明授权公开(公告)号：US07562272B2
公开(公告)日：2009-07-14
申请号：US11245308
申请日：2005-10-06
IPC分类号： G01R31/28
摘要： An apparatus and method for using electrical fuses (eFuses) to store phase-locked loop (PLL) configuration data are provided. With the apparatus and method, a portion of the eFuses present in the integrated circuit are reserved for the PLL configuration data. Upon power up, a power up controller and eFuse controller direct the sensing and serial transfer of the data in the portion of eFuses to the PLL under the reference clock. When the transfer is complete, the power up controller directs the PLL logic to load the configuration data and start. The mechanism of the present invention allows manufacturing to tailor the PLL configuration on a given device based on the characteristics of that device and its intended usage. Thus, the same PLL may be used in the same or different architectures to perform different operations based on the configuration data passed into the PLL from the eFuses.
摘要翻译： 提供了使用电熔丝（eFuses）来存储锁相环（PLL）配置数据的装置和方法。 利用该装置和方法，集成电路中存在的eFus的一部分被保留用于PLL配置数据。 上电时，上电控制器和eFuse控制器将eFuse部分中的数据的感测和串行传输指引到参考时钟下的PLL。 传输完成后，上电控制器指示PLL逻辑来加载配置数据并启动。 本发明的机构允许制造基于该设备的特性及其预期用途来定制给定设备上的PLL配置。 因此，可以在相同或不同的架构中使用相同的PLL，以便根据从eFuses传入PLL的配置数据执行不同的操作。
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7.发明申请APPARATUS AND METHOD FOR ACCELERATING TEST, DEBUG AND FAILURE ANALYSIS OF A MULTIPROCESSOR DEVICE 审中-公开用于加速多处理器设备的测试，调试和故障分析的装置和方法公开(公告)号：US20070300115A1
公开(公告)日：2007-12-27
申请号：US11421518
申请日：2006-06-01
CPC分类号： G06F11/2236
摘要： An apparatus and method for accelerating test, debug and failure analysis of a multiprocessor device are provided. With the apparatus and method, on-chip trace logic is utilized to receive internal signals from logic provided in modules of the multiprocessor device. The modules are preferably copies of one another such that, given the same inputs, each module should operate in the same manner and generate the same output as long as the modules are operating properly. The modules are provided with the same inputs and the internal signals of the modules are traced using an on-chip trace bus and on-chip trace logic analyzer to perform the trace. The internal signals from one module are compared against another module so as to determine if there is any discrepancy which would indicate a fault. Additional pairs of modules may be compared to pinpoint a faulty module that is the source of the fault.
摘要翻译： 提供了一种用于加速多处理器设备的测试，调试和故障分析的设备和方法。 利用该装置和方法，利用片上跟踪逻辑来从多处理器设备的模块中提供的逻辑接收内部信号。 这些模块优选地是彼此的副本，使得在给定相同的输入的情况下，每个模块应该以相同的方式操作并产生相同的输出，只要模块正常运行即可。 模块提供相同的输入，并使用片上跟踪总线和片上跟踪逻辑分析仪跟踪模块的内部信号，以执行跟踪。 将来自一个模块的内部信号与另一个模块进行比较，以确定是否存在指示故障的差异。 可以对额外的模块对进行比较，以确定故障源的故障模块。
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8.发明申请Method and Apparatus for Logic Built In Self Test (LBIST) Fault Detection in Multi-Core Processors 审中-公开多核处理器中自检逻辑（LBIST）故障检测方法与装置公开(公告)号：US20090089636A1
公开(公告)日：2009-04-02
申请号：US11865153
申请日：2007-10-01
IPC分类号： G06F11/263 , G06F11/25
CPC分类号： G01R31/318533 , G06F11/2242
摘要： A method, system, and computer program product for identifying failures in multi-core processors, utilizing logic built-in self test (LBIST) technology. Multi-core processors, having LBIST and pseudo-random pattern generator (PRPG) circuitry, are tested. Controlled by the LBIST control logic, PRPG inputs a test pattern into scan chains within the cores of each device. A new test pattern is generated and executed during the scan shift phase of each LBIST loop. Logic output generated by each scan chain in the core is compared to other core logic output. Failures within the multi-core processors are determined by whether the logic output generated from a core, within a latch sequence, does not match the logic output of the other cores. If logic output, from a core within a latch sequence, does not match, then the latch number, loop number, and latch values are recorded as failed.
摘要翻译： 一种利用逻辑内置自检（LBIST）技术识别多核处理器故障的方法，系统和计算机程序产品。 已经测试了具有LBIST和伪随机模式发生器（PRPG）电路的多核处理器。 由LBIST控制逻辑控制，PRPG将测试图案输入到每个设备内核的扫描链中。 在每个LBIST循环的扫描转换阶段期间，生成并执行新的测试图案。 核心中的每个扫描链产生的逻辑输出与其他核心逻辑输出进行比较。 多内核处理器内的故障是由锁存器序列中的核心产生的逻辑输出与其他内核的逻辑输出是否匹配来确定。 如果逻辑输出从锁存序列中的内核不匹配，则锁存器号，循环号和锁存值将被记录为失败。
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9.发明授权Method and apparatus for detecting frequency lock in a system including a frequency synthesizer 失效用于检测包括频率合成器的系统中的频率锁定的方法和装置公开(公告)号：US07620126B2
公开(公告)日：2009-11-17
申请号：US11236658
申请日：2005-09-27
IPC分类号： H03D3/18
摘要： A frequency synthesizer lock detection system is disclosed that distributes a frequency synthesizer output signal across a distribution network to one or more receptor circuits. The distribution network may exhibit delay and other distortion that may cause the downstream signal arriving at the receptor circuit to lose frequency lock with both the frequency synthesizer output signal and a reference clock signal that controls the frequency of the synthesizer output signal. The lock detection system tests the downstream signal to determine if the downstream signal exhibits a lock with respect to the reference clock that determines the operating frequency of the frequency synthesizer. In this manner, lock of the downstream signal to the reference clock signal may be accurately assessed in one embodiment.
摘要翻译： 公开了一种频率合成器锁定检测系统，其将分频网络上的频率合成器输出信号分配到一个或多个接收器电路。 分配网络可能表现出延迟和其他失真，这些失真可能导致下游信号到达接收器电路，同时使用频率合成器输出信号和控制合成器输出信号频率的参考时钟信号来失去频率锁定。 锁定检测系统测试下行信号以确定下游信号是否相对于确定频率合成器的工作频率的参考时钟呈现锁定。 以这种方式，可以在一个实施例中精确地评估下行信号到参考时钟信号的锁定。
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10.发明申请公开(公告)号：US20080229166A1
公开(公告)日：2008-09-18
申请号：US12129030
申请日：2008-05-29
CPC分类号： G06F11/2236
摘要： A mechanism for accelerating test, debug and failure analysis of a multiprocessor device is provided. With the mechanism, on-chip trace logic is utilized to receive internal signals from logic provided in modules of the multiprocessor device. The modules are preferably copies of one another such that, given the same inputs, each module should operate in the same manner and generate the same output as long as the modules are operating properly. The modules are provided with the same inputs and the internal signals of the modules are traced using an on-chip trace bus and on-chip trace logic analyzer to perform the trace. The internal signals from one module are compared against another module so as to determine if there is any discrepancy which would indicate a fault. Additional pairs of modules may be compared to pinpoint a faulty module that is the source of the fault.
摘要翻译： 提供了一种用于加速多处理器设备的测试，调试和故障分析的机制。 利用该机制，利用片上跟踪逻辑来从多处理器设备的模块中提供的逻辑接收内部信号。 这些模块优选地是彼此的副本，使得在给定相同的输入的情况下，每个模块应该以相同的方式操作并产生相同的输出，只要模块正常运行即可。 模块提供相同的输入，并使用片上跟踪总线和片上跟踪逻辑分析仪跟踪模块的内部信号，以执行跟踪。 将来自一个模块的内部信号与另一个模块进行比较，以确定是否存在指示故障的差异。 可以对额外的模块对进行比较，以确定故障源的故障模块。
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