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1.发明授权Method and apparatus for detecting frequency lock in a system including a frequency synthesizer 失效用于检测包括频率合成器的系统中的频率锁定的方法和装置公开(公告)号：US07620126B2
公开(公告)日：2009-11-17
申请号：US11236658
申请日：2005-09-27
IPC分类号： H03D3/18
摘要： A frequency synthesizer lock detection system is disclosed that distributes a frequency synthesizer output signal across a distribution network to one or more receptor circuits. The distribution network may exhibit delay and other distortion that may cause the downstream signal arriving at the receptor circuit to lose frequency lock with both the frequency synthesizer output signal and a reference clock signal that controls the frequency of the synthesizer output signal. The lock detection system tests the downstream signal to determine if the downstream signal exhibits a lock with respect to the reference clock that determines the operating frequency of the frequency synthesizer. In this manner, lock of the downstream signal to the reference clock signal may be accurately assessed in one embodiment.
摘要翻译： 公开了一种频率合成器锁定检测系统，其将分频网络上的频率合成器输出信号分配到一个或多个接收器电路。 分配网络可能表现出延迟和其他失真，这些失真可能导致下游信号到达接收器电路，同时使用频率合成器输出信号和控制合成器输出信号频率的参考时钟信号来失去频率锁定。 锁定检测系统测试下行信号以确定下游信号是否相对于确定频率合成器的工作频率的参考时钟呈现锁定。 以这种方式，可以在一个实施例中精确地评估下行信号到参考时钟信号的锁定。
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2.发明授权Information handling system capable of detecting frequency lock of signals downstream from a signal synthesized by frequency synthesizer 失效信号处理系统能够检测由频率合成器合成的信号下行信号的频率锁定公开(公告)号：US07590194B2
公开(公告)日：2009-09-15
申请号：US11236834
申请日：2005-09-27
IPC分类号： H03D3/18
摘要： An information handling system including a frequency synthesizer lock detection system is disclosed that distributes a frequency synthesizer output signal across a distribution network to one or more receptor circuits. The distribution network may exhibit delay and other distortion that may cause the downstream signal arriving at the receptor circuit to lose frequency lock with both the frequency synthesizer output signal and a reference clock signal that controls the frequency of the synthesizer output signal. The lock detection system tests the downstream signal to determine if the downstream signal exhibits a lock with respect to the reference clock that determines the operating frequency of the frequency synthesizer. In this manner, lock of the downstream signal to the reference clock signal may be accurately assessed in one embodiment.
摘要翻译： 公开了一种包括频率合成器锁定检测系统的信息处理系统，其将分频网络上的频率合成器输出信号分配到一个或多个接收器电路。 分配网络可能表现出延迟和其他失真，这些失真可能导致下游信号到达接收器电路，同时使用频率合成器输出信号和控制合成器输出信号频率的参考时钟信号来失去频率锁定。 锁定检测系统测试下行信号以确定下游信号是否相对于确定频率合成器的工作频率的参考时钟呈现锁定。 以这种方式，可以在一个实施例中精确地评估下行信号到参考时钟信号的锁定。
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3.发明授权System for automatically selecting intermediate power supply voltages for intermediate level shifters 失效用于自动选择中间电平转换器的中间电源电压的系统公开(公告)号：US07747892B2
公开(公告)日：2010-06-29
申请号：US12036936
申请日：2008-02-25
IPC分类号： G06F1/04
CPC分类号： H03K19/017581 , H03K19/00323 , H03K19/00346
摘要： The present invention provides for a system comprising a level shifter configured to receive a first clock signal from a first power domain, to receive a counter signal, to select one of a plurality of intermediate voltages in response to the received counter signal, and to generate a second clock signal in response to the received first clock signal and the selected intermediate voltage. A counter is coupled to the level shifter and configured to receive a divided clock signal and a comparison result signal, and to generate the counter signal in response to the received divided clock signal and comparison result signal. A divider is coupled to the counter and configured to receive the first clock signal and to generate the divided clock signal in response to the received first clock signal. A filter is coupled to the level shifter and configured to receive the second clock signal and to generate a first comparison signal in response to the received second clock signal. A fixed potential is configured to generate a second comparison signal. A comparator is coupled to the filter, the fixed potential, and the counter and configured to receive the first comparison signal and the second comparison signal, and to generate the comparison result signal in response to the received first comparison signal and the second comparison signal.
摘要翻译： 本发明提供了一种系统，包括电平移位器，其被配置为从第一功率域接收第一时钟信号，以接收计数器信号，以响应于所接收的计数器信号选择多个中间电压中的一个，并产生 响应于所接收的第一时钟信号和所选择的中间电压的第二时钟信号。 计数器耦合到电平移位器并被配置为接收分频时钟信号和比较结果信号，并且响应于接收到的分频时钟信号和比较结果信号产生计数器信号。 分频器耦合到计数器并且被配置为接收第一时钟信号并响应于接收到的第一时钟信号产生分频时钟信号。 滤波器耦合到电平移位器并且被配置为接收第二时钟信号并响应于所接收的第二时钟信号产生第一比较信号。 固定电位被配置为产生第二比较信号。 比较器耦合到滤波器，固定电位和计数器，并且被配置为接收第一比较信号和第二比较信号，并且响应于接收的第一比较信号和第二比较信号产生比较结果信号。
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4.发明授权Method for controlling operation of microprocessor which performs duty cycle correction process 失效用于控制执行占空比校正处理的微处理器的操作的方法公开(公告)号：US07716516B2
公开(公告)日：2010-05-11
申请号：US11471819
申请日：2006-06-21
申请人： Yosuke Muraki , Tetsuji Tamura , Iwao Takiguchi , Makoto Aikawa , Eskinder Hailu , Byron Lee Krauter , Stephen Douglas Weitzel , Jieming Qi , Kazuhiko Miki , David William Boerstler , Gilles Gervais , Kirk David Peterson , Robert Walter Berry, Jr. , Sang Hoo Dhong
发明人： Yosuke Muraki , Tetsuji Tamura , Iwao Takiguchi , Makoto Aikawa , Eskinder Hailu , Byron Lee Krauter , Stephen Douglas Weitzel , Jieming Qi , Kazuhiko Miki , David William Boerstler , Gilles Gervais , Kirk David Peterson , Robert Walter Berry, Jr. , Sang Hoo Dhong
CPC分类号： G06F1/04
摘要： A technology for supplying a power supply voltage to a microprocessor. Before normal arithmetic processing of the microprocessor, duty cycle correction process for adjusting the duty cycle of a clock signal inside the microprocessor is performed. In the duty cycle correction process for adjusting the duty cycle, the duty cycle of the clock signal is adjusted so as to minimize the power voltage at which the microprocessor is still operable.
摘要翻译： 用于向微处理器提供电源电压的技术。 在微处理器的正常运算处理之前，执行用于调整微处理器内的时钟信号占空比的占空比校正处理。 在用于调整占空比的占空比校正处理中，调整时钟信号的占空比以使微处理器仍然可操作的电源电压最小化。
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5.发明授权Duty cycle measurement method and apparatus that operates in a calibration mode and a test mode 有权在校准模式和测试模式下工作的占空比测量方法和装置公开(公告)号：US07595675B2
公开(公告)日：2009-09-29
申请号：US11381031
申请日：2006-05-01
IPC分类号： H03K5/04
CPC分类号： G01R31/31727
摘要： The disclosed methodology and apparatus measure the duty cycle of a reference clock signal that a clock circuit supplies to a duty cycle measurement (DCM) circuit. In one embodiment, the DCM circuit includes a capacitor driven by a charge pump. The reference clock signal drives the charge pump. The clock circuit varies the duty cycle of the reference clock signal among a number of known duty cycle values. The DCM circuit stores resultant capacitor voltage values corresponding to each of the known duty cycle values in a data store. The DCM circuit applies a test clock signal having an unknown duty cycle to the capacitor via the charge pump, thus charging the capacitor to a new voltage value that corresponds to the duty cycle of the test clock signal. Control software accesses the data store to determine the duty cycle to which the test clock signal corresponds.
摘要翻译： 所公开的方法和装置测量时钟电路提供给占空比测量（DCM）电路的参考时钟信号的占空比。 在一个实施例中，DCM电路包括由电荷泵驱动的电容器。 参考时钟信号驱动电荷泵。 时钟电路在多个已知的占空比值之间改变参考时钟信号的占空比。 DCM电路将对应于每个已知占空比值的合成电容电压值存储在数据存储器中。 DCM电路通过电荷泵向电容器施加具有未知占空比的测试时钟信号，从而将电容器充电到对应于测试时钟信号占空比的新电压值。 控制软件访问数据存储，以确定测试时钟信号对应的占空比。
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公开(公告)号：US07330061B2
公开(公告)日：2008-02-12
申请号：US11381050
申请日：2006-05-01
IPC分类号： H03K5/04
CPC分类号： H03K5/1565
摘要： The disclosed methodology and apparatus measure and correct the duty cycle of a reference clock signal that a clock circuit supplies to a duty cycle measurement (DCM) circuit. In one embodiment, the DCM circuit includes a capacitor driven by a charge pump. The reference clock signal drives the charge pump. The clock circuit varies the duty cycle of the reference clock signal among a number of known duty cycle values. The DCM circuit stores resultant capacitor voltage values corresponding to each of the known duty cycle values in a data store. The DCM circuit applies a test clock signal having an unknown duty cycle to the capacitor via the charge pump, thus charging the capacitor to a new voltage value that corresponds to the duty cycle of the test clock signal. Control software accesses the data store to determine the duty cycle to which the test clock signal corresponds, thus providing a measured duty cycle. The apparatus generates an error signal when the measured duty cycle varies from a predetermined duty cycle. The apparatus includes a variable duty cycle clock generator that alters the duty cycle of the test clock signal to reduce the error.
摘要翻译： 所公开的方法和装置测量并校正时钟电路提供给占空比测量（DCM）电路的参考时钟信号的占空比。 在一个实施例中，DCM电路包括由电荷泵驱动的电容器。 参考时钟信号驱动电荷泵。 时钟电路在多个已知的占空比值之间改变参考时钟信号的占空比。 DCM电路将对应于每个已知占空比值的合成电容电压值存储在数据存储器中。 DCM电路通过电荷泵向电容器施加具有未知占空比的测试时钟信号，从而将电容器充电到对应于测试时钟信号占空比的新电压值。 控制软件访问数据存储器以确定测试时钟信号对应的占空比，从而提供测量的占空比。 当测量的占空比从预定的占空比变化时，该装置产生误差信号。 该装置包括可变占空比时钟发生器，其改变测试时钟信号的占空比以减少误差。
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7.发明申请Clock Duty Cycle Measurement with Charge Pump Without Using Reference Clock Calibration 失效使用电荷泵进行时钟占空比测量，不使用参考时钟校准公开(公告)号：US20090326862A1
公开(公告)日：2009-12-31
申请号：US12163081
申请日：2008-06-27
CPC分类号： H03K5/1565
摘要： Embodiments of the disclosure provide systems and methods for clock duty cycle measurement. A clock signal and a complement of the clock signal are provided to a charge pump during first and second predetermined timing windows. A charge pump is operable to generate first and second output voltages in response to the clock signal and the complement of the clock signal during the first and second timing windows, respectively. In addition a predetermined positive voltage and a ground voltage are applied to the charge pump during predetermined third and fourth timing windows, respectively. The charge pump is operable to generate third and fourth output voltage signals corresponding to the predetermined positive and ground voltages during the third and fourth timing windows, respectively. The first, second, third and fourth voltages are then used to calculate the duty cycle of the clock.
摘要翻译： 本公开的实施例提供了用于时钟占空比测量的系统和方法。 时钟信号和时钟信号的补码在第一和第二预定定时窗口期间提供给电荷泵。 电荷泵可操作以分别在第一和第二定时窗口期间响应于时钟信号和时钟信号的补码产生第一和第二输出电压。 此外，预定的正电压和接地电压分别在预定的第三和第四定时窗口期间施加到电荷泵。 电荷泵可操作以分别在第三和第四定时窗口期间产生对应于预定正电压和接地电压的第三和第四输出电压信号。 然后，使用第一，第二，第三和第四电压来计算时钟的占空比。
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8.发明授权System and method automatically selecting intermediate power supply voltages for intermediate level shifters 失效系统和方法自动选择中间电平转换器的中间电源电压公开(公告)号：US07392419B2
公开(公告)日：2008-06-24
申请号：US11171756
申请日：2005-06-30
IPC分类号： G06F1/04
CPC分类号： H03K19/017581 , H03K19/00323 , H03K19/00346
摘要： The present invention provides for a system comprising a level shifter configured to receive a first clock signal from a first power domain, to receive a counter signal, to select one of a plurality of intermediate voltages in response to the received counter signal, and to generate a second clock signal in response to the received first clock signal and the selected intermediate voltage. A counter is coupled to the level shifter and configured to receive a divided clock signal and a comparison result signal, and to generate the counter signal in response to the received divided clock signal and comparison result signal. A divider is coupled to the counter and configured to receive the first clock signal and to generate the divided clock signal in response to the received first clock signal. A filter is coupled to the level shifter and configured to receive the second clock signal and to generate a first comparison signal in response to the received second clock signal. A fixed potential is configured to generate a second comparison signal. A comparator is coupled to the filter, the fixed potential, and the counter and configured to receive the first comparison signal and the second comparison signal, and to generate the comparison result signal in response to the received first comparison signal and the second comparison signal.
摘要翻译： 本发明提供了一种系统，包括电平移位器，其被配置为从第一功率域接收第一时钟信号，以接收计数器信号，以响应于所接收的计数器信号选择多个中间电压中的一个，并且产生 响应于所接收的第一时钟信号和所选择的中间电压的第二时钟信号。 计数器耦合到电平移位器并被配置为接收分频时钟信号和比较结果信号，并且响应于接收到的分频时钟信号和比较结果信号产生计数器信号。 分频器耦合到计数器并且被配置为接收第一时钟信号并响应于接收到的第一时钟信号产生分频时钟信号。 滤波器耦合到电平移位器并且被配置为接收第二时钟信号并响应于所接收的第二时钟信号产生第一比较信号。 固定电位被配置为产生第二比较信号。 比较器耦合到滤波器，固定电位和计数器，并且被配置为接收第一比较信号和第二比较信号，并且响应于接收的第一比较信号和第二比较信号产生比较结果信号。
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9.发明申请SYSTEM FOR AUTOMATICALLY SELECTING INTERMEDIATE POWER SUPPLY VOLTAGES FOR INTERMEDIATE LEVEL SHIFTERS 失效用于自动选择中级电平变送器的中间电源电压的系统公开(公告)号：US20080143419A1
公开(公告)日：2008-06-19
申请号：US12036936
申请日：2008-02-25
IPC分类号： H03L5/00
CPC分类号： H03K19/017581 , H03K19/00323 , H03K19/00346
摘要： The present invention provides for a system comprising a level shifter configured to receive a first clock signal from a first power domain, to receive a counter signal, to select one of a plurality of intermediate voltages in response to the received counter signal, and to generate a second clock signal in response to the received first clock signal and the selected intermediate voltage. A counter is coupled to the level shifter and configured to receive a divided clock signal and a comparison result signal, and to generate the counter signal in response to the received divided clock signal and comparison result signal. A divider is coupled to the counter and configured to receive the first clock signal and to generate the divided clock signal in response to the received first clock signal. A filter is coupled to the level shifter and configured to receive the second clock signal and to generate a first comparison signal in response to the received second clock signal. A fixed potential is configured to generate a second comparison signal. A comparator is coupled to the filter, the fixed potential, and the counter and configured to receive the first comparison signal and the second comparison signal, and to generate the comparison result signal in response to the received first comparison signal and the second comparison signal.
摘要翻译： 本发明提供了一种系统，包括电平移位器，其被配置为从第一功率域接收第一时钟信号，以接收计数器信号，以响应于所接收的计数器信号选择多个中间电压中的一个，并且产生 响应于所接收的第一时钟信号和所选择的中间电压的第二时钟信号。 计数器耦合到电平移位器并被配置为接收分频时钟信号和比较结果信号，并且响应于接收到的分频时钟信号和比较结果信号产生计数器信号。 分频器耦合到计数器并且被配置为接收第一时钟信号并响应于接收到的第一时钟信号产生分频时钟信号。 滤波器耦合到电平移位器并且被配置为接收第二时钟信号并响应于所接收的第二时钟信号产生第一比较信号。 固定电位被配置为产生第二比较信号。 比较器耦合到滤波器，固定电位和计数器，并且被配置为接收第一比较信号和第二比较信号，并且响应于接收的第一比较信号和第二比较信号产生比较结果信号。
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10.发明授权Method and apparatus for measuring the relative duty cycle of a clock signal 有权用于测量时钟信号的相对占空比的方法和装置公开(公告)号：US07363178B2
公开(公告)日：2008-04-22
申请号：US11555018
申请日：2006-10-31
申请人： David William Boerstler , Eskinder Hailu , Jieming Qi , Bin Wan
发明人： David William Boerstler , Eskinder Hailu , Jieming Qi , Bin Wan
IPC分类号： G01R29/02
CPC分类号： G01R31/31922 , G01R29/0273 , G01R31/31725 , G01R31/31727
摘要： In one embodiment, the disclosed methodology and apparatus measure relative duty cycle information of a clock signal with respect to an input node as the clock signal travels to selected nodes of a clock distribution network on an electronic circuit. The apparatus operates in a benchmark mode to determine benchmark duty cycle information and then subsequently operates an a relative mode to determine relative duty cycle information of the clock signal at a selected node in comparison to the clock signal at an external input node.
摘要翻译： 在一个实施例中，当时钟信号传播到电子电路上的时钟分配网络的选定节点时，所公开的方法和装置测量相对于输入节点的时钟信号的相对占空比信息。 该装置在基准模式下操作以确定基准占空比信息，然后随后操作相对模式，以确定与外部输入节点处的时钟信号相比在所选节点处的时钟信号的相对占空比信息。
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