摘要:
An active inductor circuit includes a primary and a secondary coil and a drive circuit monolithically integrated on a common substrate to provide high-Q inductors. Each inductor circuit comprises a primary coil which carries a first current that varies with an RF input signal, and a secondary coil which carries a second current that varies with the RF input; an on-chip current source provides the second current. The inductor circuit is arranged such that there is a fixed phase difference of approximately 90° between the first and second currents, and such that the magnetic field induced by the second current compensates for energy that would otherwise be dissipated by the primary coil. When the second current is properly selected, the inductor circuit's input impedance is made purely imaginary, such that the circuit emulates an ideal inductor at a particular frequency.
摘要:
An austenitic stainless steel includes (a) 0.03 wt % to 0.12 wt % of C, (b) 0.2 wt % to 1.0 wt % of Si, (c) 7.5 wt % to 10.5 wt % of Mn, (d) 14.0 wt % to 16.0 wt % of Cr, (e) 4.05 wt % to 4.31 wt % of Ni, (f) 0.04 wt % to 0.07 wt % of N, (g) 1.0 wt % to 3.5 wt % of Cu, (h) trace amount of Mo, and the balance being Fe and incidental impurities. The austenitic stainless steel has a δ-ferrite content less than 8.5 and equal to 6.77[(d)+(h)+1.5(b)]−4.85[(e)+30(a)+30(f)+0.5(c)+0.3(g)]−52.75.
摘要:
A phase lock loop includes a calibration loop for calibrating a tank circuit for capacitance variation through process variations of manufacturing an integrated circuit including the phase lock loop. A capacitance profile for setting the frequency of the phase lock loop at a process corner, such as a typical process corner is stored in driver software or a host processor. At power up, or after an idle time, a calibration is performed at two frequencies. The capacitances of operating the phase lock loop at the two frequencies are determined and stored. During a frequency change, the capacitance of operating the phase lock loop is determined from the capacitance profile and stored capacitances. In one aspect, the capacitance of the phase lock loop is presumed to change linearly with frequency and the two stored capacitances are used to determine a difference capacitance at the selected frequency by linear interpolating between the two stored capacitances. The interpolated difference capacitance is added to the capacitance in the capacitance profile at the selected frequency to generate an operating capacitance. The capacitance of a tank circuit of the phase lock loop is set to the operating capacitance.
摘要:
A phase lock loop includes a quantization circuit that generators an out of phase noise cancellation signal from an error in a delta-sigma modulator and applies the noise cancellation signal to the charge pump. The quantization circuit includes a digital-to-analog differentiator. The digital-to-analog differentiator may be, for example, a single-bit first-order digital-to-analog differentiator, a single-bit second-order digital-to-analog differentiator, or a full M-bit binary-weighted digital to analog differentiator.
摘要:
A local oscillator (LO) buffer circuit comprises first and second LO buffers arranged in a cross coupled configuration. The first LO buffer generates in-phase output signals in response to in-phase input signals, and quadrature output signals from the second LO buffer. The second LO buffer generates the quadrature output signals in response to quadrature input signals and the in-phase output signals. The LO buffers may include inductive loads. The LO buffers may include MOS transistors or bipolar junction transistors.
摘要:
A phase lock loop (PLL) includes a calibration loop for calibrating a tank circuit for capacitance variation through process variations of manufacturing an integrated circuit including the PLL. A capacitance profile for setting the frequency of the PLL at a process comer is stored. At power up, or after an idle time, a calibration is performed at two frequencies. The capacitances of operating the phase lock loop at the two frequencies are determined and stored. During a frequency change, the capacitance of operating the PLL is determined from the capacitance profile and stored capacitances. The capacitance of the PLL is presumed to change linearly with frequency and the two stored capacitances are used to determine a difference capacitance at the selected frequency by linear interpolating between the two stored capacitances, which is added to the capacitance in the capacitance profile at the selected frequency to generate an operating capacitance.
摘要:
An austenitic stainless steel includes (a) 0.03 wt % to 0.12 wt % of C, (b) 0.2 wt % to 1.0 wt % of Si, (c) 8.55 wt % to 10.12 wt % of Mn, (d) 14.0 wt % to 16.0 wt % of Cr, (e) 4.05 wt % to 4.31 wt % of Ni, (f) 0.04 wt % to 0.07 wt % of N, (g) 1.0 wt % to 3.5 wt % of Cu, (h) trace amount of Mo, and the balance being Fe and incidental impurities. The austenitic stainless steel has a δ-ferrite content less than 8.5 and equal to 6.77[(d)+(h)+1.5(b)]−4.85[(e)+30(a)+30(f)+0.5(c)+0.3(g)]−52.75.
摘要:
An austenitic stainless steel includes (a) 0.03 wt % to 0.12 wt % of C, (b) 0.2 wt % to 1.0 wt % of Si, (c) 8.55 wt % to 10.12 wt % of Mn, (d) 14.0 wt % to 16.0 wt % of Cr, (e) 4.05 wt % to 4.31 wt % of Ni, (f) 0.04 wt % to 0.07 wt % of N, (g) 1.0 wt % to 3.5 wt % of Cu, (h) trace amount of Mo, and the balance being Fe and incidental impurities. The austenitic stainless steel has a δ-ferrite content less than 8.5 and equal to 6.77[(d)+(h)+1.5(b)]−4.85[(e)+30(a)+30(f)+0.5(c)+0.3(g)]−52.75.
摘要:
An automotive radar device and an antenna cover are disclosed. The automotive radar device includes a base, an antenna disposed on the base, and the antenna cover. The antenna cover includes a main portion and an engagement portion connected to the circumference of the main portion. The engagement portion can be engaged to the base such that the main portion covers the antenna. Therein, a thickness of the main portion along a radiation direction of the antenna is equal to half-wavelength corresponding to a center operation frequency of the antenna under a dielectric constant of the main portion. Thereby, energy radiated from the antenna can mostly pass through the main portion without excessive signal attenuation, which solves the insufficient signal intensity due to a protection cover in the prior art. Further, the main portion can be made of flexible and weather resistant material to improve its physical and chemical properties.
摘要:
A phase lock loop includes a quantization circuit that generators an out of phase noise cancellation signal from an error in a delta-sigma modulator and applies the noise cancellation signal to the charge pump. The quantization circuit includes a digital-to-analog differentiator. The digital-to-analog differentiator may be, for example, a single-bit first-order digital-to-analog differentiator, a single-bit second-order digital-to-analog differentiator, or a full M-bit binary-weighted digital to analog differentiator.