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21 条记录 (耗时 0.018 秒)

    Source synchronous CDMA bus interface
    1.
    发明授权
    Source synchronous CDMA bus interface 有权
    源同步CDMA总线接口

    公开(公告)号：US07263148B2

    公开(公告)日：2007-08-28

    申请号：US10669040

    申请日：2003-09-22

    申请人： Mau-Chung F. Chang ,  Jongsun Kim

    发明人： Mau-Chung F. Chang ,  Jongsun Kim

    IPC分类号： H04L7/00

    CPC分类号： H04B5/0012 ,  H04B5/02

    摘要： A wireless IC interconnect system and a source synchronous CDMA (SS-CDMA) bus interface facilitate interconnections between first and second IC locations. A signal conveyed using the wireless system is modulated and capacitively coupled to a transmission medium, and then capacitively coupled from the medium to a receiver which demodulates the modulated signal and provides the demodulated signal to the second IC location. Multiple signals can be conveyed simultaneously by modulating and demodulating them using multiple access algorithms such as CDMA and/or FDMA. The SS-CDMA bus interface utilizes source synchronous signaling and CDMA techniques to provide high bus concurrency and low channel latency. The interface is re-configurable, and provides multi-chip access in high-bandwidth multi-drop parallel interconnection applications. The interface employs spread spectrum multiple access schemes, which enable two or more data bits to be sent through the same channel simultaneously and successfully recovered at the receiver.

    摘要翻译： 无线IC互连系统和源同步CDMA（SS-CDMA）总线接口便于第一和第二IC位置之间的互连。 使用无线系统传送的信号被调制并电容耦合到传输介质，然后从介质电容耦合到解调调制信号的接收机，并将解调的信号提供给第二IC位置。 可以通过使用诸如CDMA和/或FDMA的多种接入算法调制和解调多个信号来同时传送多个信号。 SS-CDMA总线接口利用源同步信令和CDMA技术来提供高总线并发性和低通道延迟。 该接口可重新配置，并在高带宽多点并行互连应用中提供多芯片接入。 该接口采用扩频多址方案，使得两个或多个数据位能够通过同一信道同时发送并在接收机处成功恢复。

    Integrated tunable high efficiency power amplifier
    4.
    发明授权
    Integrated tunable high efficiency power amplifier 有权
    集成可调高效率功率放大器

    公开(公告)号：US06232841B1

    公开(公告)日：2001-05-15

    申请号：US09346097

    申请日：1999-07-01

    申请人： James L. Bartlett ,  Mau Chung F. Chang ,  Henry O. Marcy, 5th ,  Kenneth D. Pedrotti ,  David R. Pehlke ,  Charles W. Seabury ,  Jun J. Yao ,  Deepak Mehrotra ,  J. L. Julian Tham

    发明人： James L. Bartlett ,  Mau Chung F. Chang ,  Henry O. Marcy, 5th ,  Kenneth D. Pedrotti ,  David R. Pehlke ,  Charles W. Seabury ,  Jun J. Yao ,  Deepak Mehrotra ,  J. L. Julian Tham

    IPC分类号： H03F304

    CPC分类号： H03F3/2176 ,  H01H59/0009

    摘要： Power amplifiers having reactive networks (such as classes C, C-E, E and F) employ tunable reactive devices in their reactive networks, with the reactive devices respective reactance values capable of being adjusted by means of respective control signals. The tunable reactive devices are made from micro-electromechanical (MEM) devices capable of being integrated with the control circuitry needed to produce the control signals and other amplifier components on a common substrate. The reactive components have high Q values across their adjustment range, enabling the amplifier to produce an output with a low harmonic content over a wide range of input signal frequencies, and a frequency agile, high quality output. The invention can be realized on a number of foundry technologies.

    摘要翻译： 具有无功网络（例如类C，C-E，E和F）的功率放大器在其无功网络中采用可调谐无功装置，其中无功装置可以通过相应的控制信号来调整各自的电抗值。 可调谐无功装置由能够与在公共基板上产生控制信号和其它放大器部件所需的控制电路集成的微机电（MEM）器件制成。 无功分量在其调节范围内具有高Q值，使得放大器能够在宽范围的输入信号频率以及频率灵敏，高质量输出下产生具有低谐波含量的输出。 本发明可以通过多种铸造技术实现。

    Integrated variable gain power amplifier and method
    5.
    发明授权
    Integrated variable gain power amplifier and method 失效
    集成可变增益功率放大器及方法

    公开(公告)号：US5834975A

    公开(公告)日：1998-11-10

    申请号：US815694

    申请日：1997-03-12

    申请人： James L. Bartlett ,  Mau Chung F. Chang ,  J. Aiden Higgins ,  Henry O. Marcy, 5th ,  Deepak Mehrotra ,  Kenneth D. Pedrotti ,  David R. Pehlke ,  Charles W. Seabury ,  J. L. Julian Tham ,  Jun J. Yao

    发明人： James L. Bartlett ,  Mau Chung F. Chang ,  J. Aiden Higgins ,  Henry O. Marcy, 5th ,  Deepak Mehrotra ,  Kenneth D. Pedrotti ,  David R. Pehlke ,  Charles W. Seabury ,  J. L. Julian Tham ,  Jun J. Yao

    IPC分类号： H03G1/00 ,  H03G3/30 ,  H03F3/68

    CPC分类号： H03F3/72 ,  H03F1/0277 ,  H03F3/211 ,  H03G1/0088

    摘要： An integrated, variable gain microwave frequency power amplifier comprises a number of individual amplifier stages which contain microwave frequency active devices. Each stage is fed with a common input signal, and the individual stage outputs are connected to respective micro-electromechanical (MEM) switches which, when closed, connect the individual outputs together to form the power amplifier's output. The power amplifier's gain is determined by the number of outputs connected together. The preferred switch provides low insertion loss and excellent electrical isolation, enabling a number of amplifier stages to be efficiently interconnected to provide a wide dynamic range power amplifier. The switches are preferably integrated on a common substrate with the active devices, eliminating the need for wire bonds and reducing parasitic capacitances. A variable impedance network comprising a number of impedance matching networks selected using MEM switches can be connected to and integrated with a variable gain power amplifier to provide impedance matching that is appropriate for each of the power amplifier's possible output power levels.

    摘要翻译： 集成的可变增益微波频率功率放大器包括多个单独的放大器级，其包含微波频率有源器件。 每个级馈入一个公共输入信号，并且各个级输出连接到相应的微机电（MEM）开关，当关闭时，各个输出端连接在一起形成功率放大器的输出。 功率放大器的增益取决于连接在一起的输出数量。 优选的开关提供低插入损耗和优异的电隔离，使得能够高效地互连多个放大器级，以提供宽动态范围功率放大器。 这些开关优选地与有源器件集成在公共衬底上，消除了对引线键合的需要并降低寄生电容。 包括使用MEM开关选择的多个阻抗匹配网络的可变阻抗网络可以连接到可变增益功率放大器并与可变增益功率放大器集成，以提供适合于每个功率放大器的可能输出功率电平的阻抗匹配。

    Method of transferring a thin film to an alternate substrate
    6.
    发明授权
    Method of transferring a thin film to an alternate substrate 失效
    将薄膜转移到替代基底的方法

    公开(公告)号：US5391257A

    公开(公告)日：1995-02-21

    申请号：US165050

    申请日：1993-12-10

    申请人： Gerard J. Sullivan ,  Mary K. Szwed ,  Mau-Chung F. Chang

    发明人： Gerard J. Sullivan ,  Mary K. Szwed ,  Mau-Chung F. Chang

    IPC分类号： H01L21/762 ,  H01L21/306 ,  B44C1/22

    CPC分类号： H01L21/76256 ,  H01L21/76251 ,  H01L2221/68322 ,  H01L2221/68363 ,  Y10S117/915 ,  Y10S438/977

    摘要： A method is described for transferring a thin film of arbitrarily large area from an original substrate to an alternate substrate. An etch stop layer is provided below an epitaxial layer, for example, grown on a semiconductor substrate. In a single transfer process, the epitaxial layer is bonded to a rigid host substrate having desirable thermal, electromagnetic, and/or mechanical properties. The original growth substrate is then removed from the transferred epitaxial layer using the etch stop layer. In a double transfer process, the epitaxial layer is first bonded to a rigid and porous temporary substrate using a thermally or chemically releasable resin, for example. The original growth substrate is removed using the etch stop layer so that the original substrate side of the epitaxial layer can be bonded to a rigid host substrate, as described above. The temporary substrate is then removed using the releasable resin to leave the transferred thin film attached to the host substrate.

    摘要翻译： 描述了用于将任意大面积的薄膜从原始衬底转移到替代衬底的方法。 例如，在半导体衬底上生长的外延层下面提供蚀刻停止层。 在单次转移过程中，外延层被结合到具有期望的热，电磁和/或机械性能的刚性主体衬底上。 然后使用蚀刻停止层从转移的外延层去除原始生长衬底。 在双重转移过程中，例如，外延层首先使用热或化学上可释放的树脂结合到刚性和多孔的临时衬底上。 如上所述，使用蚀刻停止层去除原始生长衬底，使得外延层的原始衬底侧可以结合到刚性主体衬底。 然后使用可释放树脂除去临时衬底，以使转移的薄膜附着到主体衬底上。

    Self-aligned dielectric assisted planarization process
    7.
    发明授权
    Self-aligned dielectric assisted planarization process 失效
    自对准介质辅助平面化工艺

    公开(公告)号：US4996165A

    公开(公告)日：1991-02-26

    申请号：US341464

    申请日：1989-04-21

    申请人： Mau-Chung F. Chang ,  Peter M. Asbeck

    发明人： Mau-Chung F. Chang ,  Peter M. Asbeck

    IPC分类号： H01L21/28 ,  H01L21/331 ,  H01L21/768

    CPC分类号： H01L29/66318 ,  H01L21/28 ,  H01L21/76819 ,  Y10S148/043 ,  Y10S148/072 ,  Y10S148/075

    摘要： A method for planarizing surfaces in multi-layered semiconductor structures using elevated features in the form of semiconductor materials, such as for forming heterojunctions, or interconnection metal. A process of forming the features includes leaving residual photoresist on the features. After feature formation and definition of transistor or other structure locations, dielectric material is deposited across the structure. Remaining photoresist is subsequently removed along with dielectric deposited thereon leaving dielectric between the features. A layer of polyimide is spun on the structure and into depressions between the dielectric and features. Typically material deposition, etching, dielectric backfilling and spin-coating steps are repeated until a predetermined number of contact or conductivity regions or interconnection metal layers are formed in the desired multi-layered structure. In addition, intermediate etching steps may be employed for defining one or more transistor base or collector locations and metal or alloys deposited therein. Height variations in the resulting planar surface are controllable to within a fraction of a micron or less.

    摘要翻译： 使用诸如用于形成异质结或互连金属的半导体材料形式的升高特征来平坦化多层半导体结构中的表面的方法。 形成特征的过程包括将残留光致抗蚀剂留在特征上。 在特征形成和晶体管或其他结构位置的定义之后，电介质材料跨结构沉积。 其余的光致抗蚀剂随后与其上沉积的电介质一起去除，留下特征之间的电介质。 一层聚酰亚胺在结构上旋转并且在电介质和特征之间形成凹陷。 通常重复材料沉积，蚀刻，电介质回填和旋涂步骤，直到在期望的多层结构中形成预定数量的接触或导电区域或互连金属层。 此外，中间蚀刻步骤可以用于限定一个或多个晶体管基极或集电极位置以及沉积在其中的金属或合金。 所得平面表面的高度变化可控制在微米或更小的分数之内。

    Dual lift-off self aligning process for making heterojunction bipolar transistors
    8.
    发明授权
    Dual lift-off self aligning process for making heterojunction bipolar transistors 失效
    用于制造异质结双极晶体管的双重剥离自对准工艺

    公开(公告)号：US4731340A

    公开(公告)日：1988-03-15

    申请号：US17957

    申请日：1987-02-24

    申请人： Mau-Chung F. Chang ,  Peter M. Asbeck

    发明人： Mau-Chung F. Chang ,  Peter M. Asbeck

    IPC分类号： H01L21/027 ,  H01L21/331 ,  H01L29/06 ,  H01L29/08 ,  H01L29/737 ,  H01L21/265

    CPC分类号： H01L29/66318 ,  H01L21/0272 ,  H01L29/0649 ,  H01L29/0821 ,  H01L29/7371 ,  Y10S438/951

    摘要： A dual lift-off technique is used to provide self-alignment of the emitter area, the emitter contact, and the base contact of a heterojunction, bipolar transistor. A photoresist pattern which defines an emitter adjacent a base contact is formed on a suitable heterojunction bipolar semiconductor wafer. A base contact is formed by etching through the first semiconductor to the heterojunction and depositing metal on the second semiconductor. Dielectric is then deposited on the base contact. The photoresist is then lifted off with its dual covering of dielectric and metal. The emitter contact metal can then be deposited without requiring critical alignment because the base contact is covered with dielectric.

    摘要翻译： 双重剥离技术用于提供异质结双极晶体管的发射极区域，发射极接触和基极接触的自对准。 在合适的异质结双极半导体晶片上形成限定邻近基极触点的发射极的光致抗蚀剂图案。 通过将第一半导体蚀刻到异质结并在第二半导体上沉积金属形成基极接触。 然后将电介质沉积在基底触点上。 然后用其电介质和金属的双重覆盖物剥离光致抗蚀剂。 然后可以沉积发射极接触金属，而不需要进行临界对准，因为基极接触被电介质覆盖。

    On-chip inductor using active magnetic energy recovery
    9.
    发明授权
    On-chip inductor using active magnetic energy recovery 有权
    片上电感采用有源磁能回收

    公开(公告)号：US06608361B2

    公开(公告)日：2003-08-19

    申请号：US09999709

    申请日：2001-10-30

    申请人： Mau-Chung F. Chang ,  Yi-Cheng Wu

    发明人： Mau-Chung F. Chang ,  Yi-Cheng Wu

    IPC分类号： H01L2900

    CPC分类号： H03H11/48 ,  H01F17/0006

    摘要： An active inductor circuit includes a primary and a secondary coil and a drive circuit monolithically integrated on a common substrate to provide high-Q inductors. Each inductor circuit comprises a primary coil which carries a first current that varies with an RF input signal, and a secondary coil which carries a second current that varies with the RF input; an on-chip current source provides the second current. The inductor circuit is arranged such that there is a fixed phase difference of approximately 90° between the first and second currents, and such that the magnetic field induced by the second current compensates for energy that would otherwise be dissipated by the primary coil. When the second current is properly selected, the inductor circuit's input impedance is made purely imaginary, such that the circuit emulates an ideal inductor at a particular frequency.

    摘要翻译： 有源电感器电路包括初级线圈和次级线圈以及整体集成在公共基板上以提供高Q电感器的驱动电路。 每个电感器电路包括承载随RF输入信号变化的第一电流的初级线圈和承载随着RF输入而变化的第二电流的次级线圈; 片上电流源提供第二电流。 电感器电路布置成使得在第一和第二电流之间存在约90°的固定相位差，并且使得由第二电流感应的磁场补偿否则将由初级线圈消散的能量。 当适当地选择第二电流时，电感器电路的输入阻抗被制成纯虚数，使得电路以特定频率仿真理想电感器。