Low-height coupled inductors
    1.
    发明授权

    公开(公告)号:US11615915B2

    公开(公告)日:2023-03-28

    申请号:US16593108

    申请日:2019-10-04

    IPC分类号: H01F27/24 H01F27/34 H01F27/29

    摘要: A coupled inductor includes a ladder magnetic core including (a) a first rail and a second rail separated from each other in a first direction and (b) a plurality of rungs separated from each other in a second direction. The second direction is orthogonal to the first direction, and each rung of the plurality of rungs is disposed between the first rail and the second rail in the first direction. The coupled inductor further includes a plurality of windings, where each winding of the plurality of windings is partially wound around a respective one of the plurality of rungs such that each winding of the plurality of windings does not overlap with itself when the coupled inductor is viewed cross-sectionally in a third direction. The third direction is orthogonal to each of the first direction and the second direction.

    Multi-level switching power converters including bypass transistors and associated methods

    公开(公告)号:US10734898B1

    公开(公告)日:2020-08-04

    申请号:US16020289

    申请日:2018-06-27

    IPC分类号: H02M3/158 H02M1/088 H02M1/00

    摘要: A multi-level switching power converter includes a string of N upper transistors and a string of N lower transistors, where N is an integer greater than one. The N upper transistors are electrically coupled in series between a first power node and a switching node, and the N lower transistors are electrically coupled in series between the switching node and a reference node. The multi-level switching power converter further includes N−1 flying capacitors, an inductor, a bypass transistor, and a controller. The bypass transistor is electrically coupled between the switching node and the reference node. The controller is configured to (a) control switching of the N upper transistors and the N lower transistors and (b) cause the bypass transistor to operate in its on state in response to all of the N lower transistors operating in their respective on states.

    SWITCHING CIRCUITS HAVING MULTIPLE OPERATING MODES AND ASSOCIATED METHODS
    4.
    发明申请
    SWITCHING CIRCUITS HAVING MULTIPLE OPERATING MODES AND ASSOCIATED METHODS 审中-公开
    具有多种操作模式和相关方法的切换电路

    公开(公告)号:US20170018931A1

    公开(公告)日:2017-01-19

    申请号:US15209154

    申请日:2016-07-13

    IPC分类号: H02J3/38 H02J3/14

    摘要: A method for controlling a switching circuit including an input port electrically coupled to a photovoltaic device and an output port electrically coupled to a load includes (1) entering a voltage limiting operating mode and (2) in the voltage limiting operating mode (i) causing a control switching device of the switching circuit to repeatedly switch between its conductive and non-conductive states in a manner which limits magnitude of an output voltage to a maximum voltage value, the output voltage being a voltage across the output port, and (ii) varying the maximum voltage value as a function of magnitude of an output current, the output current being a current flowing through the output port.

    摘要翻译: 一种用于控制开关电路的方法,该开关电路包括电耦合到光伏器件的输入端口和电耦合到负载的输出端口包括(1)进入电压限制操作模式和(2)在限压操作模式(i)中引起 所述开关电路的控制切换装置以将输出电压的幅度限制为最大电压值的方式重复地在其导通状态和非导通状态之间切换,所述输出电压是所述输出端口两端的电压,以及(ii) 将最大电压值改变为输出电流的大小的函数,输出电流是流过输出端口的电流。

    Multi-level switching power converters including bypass transistors and associated methods

    公开(公告)号:US11088620B1

    公开(公告)日:2021-08-10

    申请号:US16917890

    申请日:2020-06-30

    IPC分类号: H02M3/158 H02M1/088 H02M1/00

    摘要: A multi-level switching power converter includes a string of N upper transistors and a string of N lower transistors, where N is an integer greater than one. The N upper transistors are electrically coupled in series between a first power node and a switching node, and the N lower transistors are electrically coupled in series between the switching node and a reference node. The multi-level switching power converter further includes N−1 flying capacitors, an inductor, a bypass transistor, and a controller. The bypass transistor is electrically coupled between the switching node and the reference node. The controller is configured to (a) control switching of the N upper transistors and the N lower transistors and (b) cause the bypass transistor to operate in its on state in response to all of the N lower transistors operating in their respective on states.