公开(公告)号：US20110241744A1

公开(公告)日：2011-10-06

申请号：US13061106

申请日：2009-08-20

申请人： Mayan Moudgill ,  Gary Nacer ,  Shenghong Wang

发明人： Mayan Moudgill ,  Gary Nacer ,  Shenghong Wang

IPC分类号： H03K3/289

CPC分类号： G06F9/30141 ,  G06F9/30116 ,  G06F9/30123

摘要： A processor register file for a multi-threaded processor is described. The processore register file includes, in one embodiment, T threads, having N b-bit wide registers. Each of the registers includes a b-bit master latch, T b-bit slave latches connected to the master latch, and a slave latch write enable connected to the slave latches. The master latch is not opened at the same time as the slave latches. In addition, only one of the slave latches is enabled at any given time. As should be apparent to those skilled in the art, T, N, and b are all integers. Other embodiments and variations are also provided.

摘要翻译： 描述用于多线程处理器的处理器寄存器文件。 在一个实施例中，处理器寄存器文件包括具有N个b位宽寄存器的T线程。 每个寄存器包括一个b位主锁存器，连接到主锁存器的T b位从属锁存器和一个从锁存器写使能，连接到从锁存器。 主锁存器不会与从动锁存器同时打开。 此外，在任何给定时间只有一个从锁存器被使能。 对于本领域技术人员来说显而易见的是，T，N和b都是整数。 还提供了其它实施例和变型。

公开(公告)号：US08471597B2

公开(公告)日：2013-06-25

申请号：US12994115

申请日：2009-05-07

申请人： Shenghong Wang ,  Mayan Moudgill ,  Gary Nacer

发明人： Shenghong Wang ,  Mayan Moudgill ,  Gary Nacer

IPC分类号： H03K19/173 ,  H03K19/00 ,  H03K19/096

CPC分类号： G06F1/32 ,  G06F1/04 ,  Y10T29/49117

摘要： A circuit is described including a clock input for at least one clock signal. Only one clock buffer is connected to the clock input to generate, based on the at least one clock signal, at least a first modified clock signal and a second modified clock signal. A plurality of flip-flops are connected to the clock buffer. Each of the flip-flops receive the first and second modified clock signals. A plurality of data inputs are each connected to at least one of the plurality of flip-flops to provide input data to the plurality of flip-flops. A plurality of data outputs each are connected to at least one of the plurality of flip-flops to provide output data from the plurality of flip-flops. Each of the plurality of flip-flops transform the input data to the output data utilizing the first modified clock signal and the second modified clock signal.

摘要翻译： 描述了包括用于至少一个时钟信号的时钟输入的电路。 只有一个时钟缓冲器被连接到时钟输入端，以便基于至少一个时钟信号产生至少第一修改时钟信号和第二修改时钟信号。 多个触发器连接到时钟缓冲器。 每个触发器接收第一和第二修改的时钟信号。 多个数据输入各自连接到多个触发器中的至少一个，以向多个触发器提供输入数据。 多个数据输出各自连接到多个触发器中的至少一个，以提供来自多个触发器的输出数据。 多个触发器中的每一个利用第一修改时钟信号和第二修改时钟信号将输入数据变换为输出数据。

公开(公告)号：US20110254588A1

公开(公告)日：2011-10-20

申请号：US12994115

申请日：2009-05-07

申请人： Gary Nacer ,  Mayan Moudgill ,  Shenghong Wang

发明人： Gary Nacer ,  Mayan Moudgill ,  Shenghong Wang

IPC分类号： G06F7/38 ,  H01R43/00 ,  H03K3/00

CPC分类号： G06F1/32 ,  G06F1/04 ,  Y10T29/49117

摘要： A circuit is described including a clock input for at least one clock signal. Only one clock buffer is connected to the clock input to generate, based on the at least one clock signal, at least a first modified clock signal and a second modified clock signal. A plurality of flip-flops are connected to the clock buffer. Each of the flip-flops receive the first and second modified clock signals. A plurality of data inputs are each connected to at least one of the plurality of flip-flops to provide input data to the plurality of flip-flops. A plurality of data outputs each are connected to at least one of the plurality of flip-flops to provide output data from the plurality of flip-flops. Each of the plurality of flip-flops transform the input data to the output data utilizing the first modified clock signal and the second modified clock signal.

摘要翻译： 描述了包括用于至少一个时钟信号的时钟输入的电路。 只有一个时钟缓冲器被连接到时钟输入端，以便基于至少一个时钟信号产生至少第一修改时钟信号和第二修改时钟信号。 多个触发器连接到时钟缓冲器。 每个触发器接收第一和第二修改的时钟信号。 多个数据输入各自连接到多个触发器中的至少一个，以向多个触发器提供输入数据。 多个数据输出各自连接到多个触发器中的至少一个，以提供来自多个触发器的输出数据。 多个触发器中的每一个利用第一修改时钟信号和第二修改时钟信号将输入数据变换为输出数据。

公开(公告)号：US20050008098A1

公开(公告)日：2005-01-13

申请号：US10615902

申请日：2003-07-10

申请人： Daniel Iancu ,  Gary Nacer ,  Stuart Stanley

发明人： Daniel Iancu ,  Gary Nacer ,  Stuart Stanley

IPC分类号： H04B1/40 ,  H04L27/06

CPC分类号： H04B1/005 ,  H04B1/406

摘要： A radio including a first channel for receiving signals at a first frequency and a second channel for receiving and transmitting signals at a second frequency. A multiplexer connects the first and second channels through an A/D and D/A converter to a digital signal processor. An oscillator is connected to and provides a common sampling frequency to the A/D and D/A converters. The digital signal processor controls the multiplexer and modifies the received digital signals to accommodate for the different carrier frequencies of the channels using the common sampling rate. A frequency synthesizer is connected to the oscillator and provides different frequency signals for the channels. A third channel may be provided for receiving and transmitting signals at a third frequency and is also connected to the multiplexer. The processor is capable of performing communication protocols for at least two of the channels simultaneously.

摘要翻译： 一种无线电设备，包括用于以第一频率接收信号的第一信道和用于以第二频率接收和发送信号的第二信道。 多路复用器通过A / D和D / A转换器将第一和第二通道连接到数字信号处理器。 振荡器连接到A / D和D / A转换器并提供公共采样频率。 数字信号处理器控制多路复用器，并使用公共采样率修改接收的数字信号以适应信道的不同载波频率。 频率合成器连接到振荡器，并为通道提供不同的频率信号。 可以提供第三通道用于以第三频率接收和发送信号，并且还连接到多路复用器。 处理器能够同时为至少两个通道执行通信协议。

公开(公告)号：US07158583B2

公开(公告)日：2007-01-02

申请号：US10615902

申请日：2003-07-10

申请人： Daniel Iancu ,  Gary Nacer ,  Stuart G. Stanley

发明人： Daniel Iancu ,  Gary Nacer ,  Stuart G. Stanley

IPC分类号： H04L27/06

CPC分类号： H04B1/005 ,  H04B1/406

摘要： A radio including a first channel for receiving signals at a first frequency and a second channel for receiving and transmitting signals at a second frequency. A multiplexer connects the first and second channels through an A/D and D/A converter to a digital signal processor. An oscillator is connected to and provides a common sampling frequency to the A/D and D/A converters. The digital signal processor controls the multiplexer and modifies the received digital signals to accommodate for the different carrier frequencies of the channels using the common sampling rate. A frequency synthesizer is connected to the oscillator and provides different frequency signals for the channels. A third channel may be provided for receiving and transmitting signals at a third frequency and is also connected to the multiplexer. The processor is capable of performing communication protocols for at least two of the channels simultaneously.

摘要翻译： 一种无线电设备，包括用于以第一频率接收信号的第一信道和用于以第二频率接收和发送信号的第二信道。 多路复用器通过A / D和D / A转换器将第一和第二通道连接到数字信号处理器。 振荡器连接到A / D和D / A转换器并提供公共采样频率。 数字信号处理器控制多路复用器，并使用公共采样率修改接收的数字信号以适应信道的不同载波频率。 频率合成器连接到振荡器，并为通道提供不同的频率信号。 可以提供第三通道用于以第三频率接收和发送信号，并且还连接到多路复用器。 处理器能够同时为至少两个通道执行通信协议。