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公开(公告)号：US20240171166A1
公开(公告)日：2024-05-23
申请号：US18493378
申请日：2023-10-24
申请人： Media Tek Inc.
发明人： Ahmed Safwat Mohamed Aboelenein Elmallah , Amr Tarek Ahmed Abdelrazik Khashaba , Mohammed Mohsen Abdulsalam Abdullatif , Tamer Mohammed Ali
CPC分类号： H03K5/14 , H03L7/099 , H03K2005/00058
摘要： A system to operate as a phase locked loop (PLL) includes a frequency synthesizer in a feedback path of the PLL and a delay line arranged to receive an output of the frequency synthesizer. A retimer subsystem is arranged to receive the output of the frequency synthesizer. A digitally controlled delay line (DCDL) is arranged to receive an output of the retimer. A phase detector is arranged to receive an output of the delay line and an output of the DCDL and to provide an error signal indicating a difference in phase of the output of the delay line relative to the output of the DCDL. A controller causes closed loop operation of the PLL during a normal operational mode and open loop operation during a calibration mode during which gain of the DCDL, defining a relationship between a control code and a resulting delay, is calibrated.
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公开(公告)号：US20240171167A1
公开(公告)日：2024-05-23
申请号：US18496495
申请日：2023-10-27
申请人： Media Tek Inc.
发明人： Ahmed Safwat Mohamed Aboelenein Elmallah , Amr Tarek Ahmed Abdelrazik Khashaba , Mohammed Mohsen Abdulsalam Abdullatif , Tamer Mohammed Ali
摘要： A digitally controlled delay device includes a plurality of first delay stages connected in series between a first input port and a first output port, and a plurality of second delay stages connected in series between a second input port and a second output port. Each first delay stage of the plurality of first delay stages includes a plurality of first delay elements and each second delay stage of the plurality of second delay stages includes a corresponding plurality of second delay elements. A controller performs complementary control based on a digital control signal by controlling one or more of the plurality of first delay elements to be in a first control state and controlling a corresponding one or more of the plurality of second delay elements to be in a second control state, opposite the first control state.
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公开(公告)号：US20240162907A1
公开(公告)日：2024-05-16
申请号：US18492518
申请日：2023-10-23
申请人： Media Tek Inc.
发明人： Ahmed Safwat Mohamed Aboelenein Elmallah , Amr Tarek Ahmed Abdelrazik Khashaba , Mohammed Mohsen Abdulsalam Abdullatif , Tamer Mohammed Ali
摘要： The techniques described herein relate to digitally controlled delay line gain calibration using error injection. An example apparatus includes a digitally controlled delay line (DCDL) with a DCDL output and configured to: receive a clock signal to be output from a voltage-controlled oscillator, and delay the clock signal to generate a first delayed clock signal. The apparatus further includes an error injection circuit with a first error injection input and a second error injection input, the first error injection input coupled to the DCDL output. The apparatus additionally includes a phase controller with a phase controller output coupled to the second error injection input, the phase controller configured to, in response to a pseudorandom binary sequence signal, instruct the error injection circuit to generate a second delayed clock signal based on a delay of the first delayed clock signal.
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4.发明公开公开(公告)号：US20240171165A1
公开(公告)日：2024-05-23
申请号：US18383511
申请日：2023-10-25
申请人： MEDIA TEK INC.
发明人： Ahmed Safwat Mohamed Aboelenein Elmallah , Mohammed Mohsen Abdulsalam Abdullatif , Tamer Mohammed Ali
IPC分类号： H03K5/1252 , H03M1/82
CPC分类号： H03K5/1252 , H03M1/82 , H03K2005/00058
摘要： A circuit or reducing fractional spurs comprises a digital to time converter (DTC) comprising multiple delay stages electrically coupled to one another in series, configured such that each delay stage is binary switched till the code exceeds cell range and then it is fully turned ON, and thereafter it is moved to the next stage, each delay stage comprising a digitally controlled delay line (DCDL) having code-dependent integrated nonlinearity (INL), with the maximal value of the INL occuring at a mid-code position; and an offset stage comprising the DCDL electrically coupled to the DTC in series, configured to generate random codes for each required time delay of the DTC to ensure the probability of landing at the mid-code position is reduced and landing point is kept as far away as possible from the mid-code position for every required time delay, thereby improving the INL and the fractional spurs.
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