公开(公告)号：US20150123206A1

公开(公告)日：2015-05-07

申请号：US14450445

申请日：2014-08-04

Applicant: MediaTek Inc.

Inventor： Cheng-Chou HUNG ,  Tung-Hsing LEE ,  Bernard Mark TENBROEK ,  Rong-Tang CHEN

IPC: H01L29/78 ,  H01L29/49 ,  H01L29/10 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/783 ,  H01L29/0649 ,  H01L29/1095 ,  H01L29/4238 ,  H01L29/4975 ,  H01L29/78615 ,  H01L29/78654 ,  H01L29/78657

Abstract: The invention provides a body-contact metal-oxide-semiconductor field effect transistor (MOSFET) device. The body-contact MOSFET device includes a substrate. An active region is disposed on the substrate. A gate strip is extended along a first direction disposed on a first portion of the active region. A source doped region and a drain doped region are disposed on a second portion and a third portion of the active region, adjacent to opposite sides of the gate strip. The opposite sides of the gate strip are extended along the first direction. A body-contact doped region is disposed on a fourth portion of the active region. The body-contact doped region is separated from the gate strip by a fifth portion of the active region. The fifth portion is not covered by any silicide features.

Abstract translation: 本发明提供一种体接触金属氧化物半导体场效应晶体管（MOSFET）器件。 体接触MOSFET器件包括衬底。 有源区设置在基板上。 栅极条沿着设置在有源区域的第一部分上的第一方向延伸。 源极掺杂区域和漏极掺杂区域设置在与栅极条的相对侧相邻的有源区域的第二部分和第三部分上。 栅极条的相对侧沿第一方向延伸。 体接触掺杂区域设置在有源区域的第四部分上。 体接触掺杂区域与有源区域的第五部分与栅极条分离。 第五部分不被任何硅化物特征覆盖。

公开(公告)号：US20210004042A1

公开(公告)日：2021-01-07

申请号：US16918601

申请日：2020-07-01

Applicant: MEDIATEK INC.

Inventor： Chien-Wei TSENG ,  Mohammed Fathey Abdelfattah HASSAN ,  Li-Shin LAI ,  Tzu-Yu YEH ,  Ming-Da TSAI ,  Bernard Mark TENBROEK

IPC: G06F1/12 ,  H03K3/037 ,  G06F1/10

Abstract: Aspects of the disclosure provide methods and apparatuses for generating an internal reset signal that is synchronous to a clock signal. In some embodiments, an apparatus includes a clock switch circuit and a plurality of serially coupled D flip-flops (DFFs). The clock switch circuit receiving the clock signal can output the clock signal in an on state and block the clock signal in an off state. The plurality of serially coupled DFFs are coupled to the clock switch circuit and driven by the clock signal. If an external reset signal is enabled, the plurality of serially coupled DFFs can enable the internal reset signal. If the external reset signal is disabled, after a predefined number of clock signal cycles, the plurality of serially coupled DFFs can disable the internal reset signal.