公开(公告)号：US09306389B2

公开(公告)日：2016-04-05

申请号：US14677508

申请日：2015-04-02

Applicant: MediaTek Inc.

Inventor： Chien-Hui Chuang

IPC: H02H9/00 ,  H02H9/04 ,  H01L27/02 ,  H03K19/003

CPC classification number: H02H9/04 ,  H01L27/0266 ,  H01L27/0277 ,  H03K19/00315

Abstract: An electrostatic discharge protection circuit is provided. First NMOS transistor is coupled to a power line. Second NMOS transistor is coupled between the first NMOS transistor and a ground. Detection unit provides a detection signal when an ESD event occurs at the power line. Trigger unit turns on the second NMOS transistor and the first NMOS transistor in sequence in response to the detection signal. Discharge path is formed from the power line to the ground via the first and second NMOS transistors. First PMOS transistor is coupled between the power line and a gate of the second NMOS transistor. Third NMOS transistor is coupled between the ground and the gate of the second NMOS transistor. Second PMOS transistor is coupled between the gates of the first and second NMOS transistors. Third PMOS transistor is coupled between the power line and the first PMOS transistor.

Abstract translation: 提供静电放电保护电路。 第一NMOS晶体管耦合到电源线。 第二NMOS晶体管耦合在第一NMOS晶体管和地之间。 当电源线发生ESD事件时，检测单元提供检测信号。 触发单元响应于检测信号依次接通第二NMOS晶体管和第一NMOS晶体管。 放电路径由电源线经由第一和第二NMOS晶体管形成到地。 第一PMOS晶体管耦合在电源线和第二NMOS晶体管的栅极之间。 第三NMOS晶体管耦合在第二NMOS晶体管的接地和栅极之间。 第二PMOS晶体管耦合在第一和第二NMOS晶体管的栅极之间。 第三PMOS晶体管耦合在电源线和第一PMOS晶体管之间。

公开(公告)号：US09543377B2

公开(公告)日：2017-01-10

申请号：US14548298

申请日：2014-11-20

Applicant: MEDIATEK INC.

Inventor： Bo-Shih Huang ,  Chien-Hui Chuang ,  Cheng-Chou Hung

IPC: H01L27/06 ,  H01L29/73 ,  H01L29/78 ,  H01L23/60 ,  H01L29/788 ,  H01L29/06 ,  H01L29/74 ,  H01L29/45

CPC classification number: H01L29/0603 ,  H01L29/0657 ,  H01L29/0688 ,  H01L29/36 ,  H01L29/45 ,  H01L29/7436

Abstract: A semiconductor device comprising a substrate is disclosed. The substrate comprises: a well of type one; a first doped region of type two, provided in the well of type one; a well of type two, adjacent to the well of type one; and a first doped region of type one, doped in the well of type two. The substrate comprises no isolating material provided in a current path formed by the first doped region of type two, the well of type one, the well of type two and the first doped region of type one.

Abstract translation: 公开了一种包括衬底的半导体器件。 基材包括：一类的孔; 设置在类型1的阱中的类型2的第一掺杂区域; 一类二井，毗邻一井; 以及掺杂在类型2的阱中的第一掺杂区域。 衬底不包括设置在由第二类型的第一掺杂区，类型二的阱，类型二的阱和类型1的第一掺杂区形成的电流路径中的隔离材料。

公开(公告)号：US20160148992A1

公开(公告)日：2016-05-26

申请号：US14548298

申请日：2014-11-20

Applicant: MEDIATEK INC.

Inventor： Bo-Shih Huang ,  Chien-Hui Chuang ,  Cheng-Chou Hung

IPC: H01L29/06 ,  H01L29/45

CPC classification number: H01L29/0603 ,  H01L29/0657 ,  H01L29/0688 ,  H01L29/36 ,  H01L29/45 ,  H01L29/7436

Abstract: A semiconductor device comprising a substrate is disclosed. The substrate comprises: a well of type one; a first doped region of type two, provided in the well of type one; a well of type two, adjacent to the well of type one; and a first doped region of type one, doped in the well of type two. The substrate comprises no isolating material provided in a current path formed by the first doped region of type two, the well of type one, the well of type two and the first doped region of type one.

Abstract translation: 公开了一种包括衬底的半导体器件。 基材包括：一类的孔; 设置在类型1的阱中的类型2的第一掺杂区域; 一类二井，毗邻一井; 以及掺杂在类型2的阱中的第一掺杂区域。 衬底不包括设置在由第二类型的第一掺杂区，类型二的阱，类型二的阱和类型1的第一掺杂区形成的电流路径中的隔离材料。

公开(公告)号：US10535647B2

公开(公告)日：2020-01-14

申请号：US15149262

申请日：2016-05-09

Applicant: MediaTek Inc.

Inventor： Yu-Jen Chen ,  Chien-Hui Chuang

IPC: H01L27/02 ,  H01L27/092 ,  H01L27/06 ,  H02H9/04

Abstract: The invention provides an ESD (Electrostatic Discharge) protection circuit including a clamp circuit, a switch element, and a detection circuit. The clamp circuit is coupled between an ESD bus and a ground node. The switch element is coupled between a supply node and the ESD bus. The detection circuit is configured to detect whether an ESD event occurs. When no ESD event occurs, the detection circuit closes the switch element, such that the ESD bus is coupled to the supply node. When the ESD event occurs, the detection circuit opens the switch element, such that the ESD bus is decoupled from the supply node.

公开(公告)号：US09806146B2

公开(公告)日：2017-10-31

申请号：US15367126

申请日：2016-12-01

Applicant: MEDIATEK INC.

Inventor： Bo-Shih Huang ,  Chien-Hui Chuang ,  Cheng-Chou Hung

IPC: H01L27/06 ,  H01L29/73 ,  H01L29/78 ,  H01L23/60 ,  H01L29/788 ,  H01L29/06 ,  H01L29/74 ,  H01L29/45 ,  H01L29/36

CPC classification number: H01L29/0603 ,  H01L29/0657 ,  H01L29/0688 ,  H01L29/36 ,  H01L29/45 ,  H01L29/7436

Abstract: A semiconductor device comprising a substrate is disclosed. The substrate comprises: a well of type one; a first doped region of type two, provided in the well of type one; a well of type two, adjacent to the well of type one; a first doped region of type one, doped in the well of type two; and a second doped region of type two, provided in the well of type one and the well of type two, not touching the first doped region of type two. The substrate comprises no isolating material provided in a current path formed by the first doped region of type two, the well of type one, the well of type two and the first doped region of type one.

公开(公告)号：US20170084685A1

公开(公告)日：2017-03-23

申请号：US15367126

申请日：2016-12-01

Applicant: MEDIATEK INC.

Inventor： Bo-Shih Huang ,  Chien-Hui Chuang ,  Cheng-Chou Hung

IPC: H01L29/06 ,  H01L29/36 ,  H01L29/45

CPC classification number: H01L29/0603 ,  H01L29/0657 ,  H01L29/0688 ,  H01L29/36 ,  H01L29/45 ,  H01L29/7436

Abstract: A semiconductor device comprising a substrate is disclosed. The substrate comprises: a well of type one; a first doped region of type two, provided in the well of type one; a well of type two, adjacent to the well of type one; a first doped region of type one, doped in the well of type two; and a second doped region of type two, provided in the well of type one and the well of type two, not touching the first doped region of type two. The substrate comprises no isolating material provided in a current path formed by the first doped region of type two, the well of type one, the well of type two and the first doped region of type one.

公开(公告)号：US09305915B2

公开(公告)日：2016-04-05

申请号：US14635255

申请日：2015-03-02

Applicant: MediaTek Inc.

Inventor： Chien-Hui Chuang

IPC: H02H9/00 ,  H01L27/02 ,  H03K19/003

CPC classification number: H01L27/0266 ,  H01L27/0277 ,  H03K19/00315

Abstract: An electrostatic discharge (ESD) protection circuit is provided. The ESD protection circuit includes a first NMOS transistor coupled to a power line, a second NMOS transistor coupled between the first transistor and a ground, a detection unit, providing a detection signal when an ESD event occurs at the power line, and a trigger unit, turning on the second NMOS transistor and the first NMOS transistor in sequence in response to the detection signal, such that a discharge path is formed from the power line to the ground via the first and second NMOS transistors. The trigger unit includes a first PMOS transistor coupled between the power line and a gate of the second NMOS transistor, a fourth resistor, and a second PMOS transistor, having a gate coupled to the cathode of the diode for receiving the detection signal.

Abstract translation: 提供静电放电（ESD）保护电路。 ESD保护电路包括耦合到电源线的第一NMOS晶体管，耦合在第一晶体管和地之间的第二NMOS晶体管，检测单元，当在电力线处发生ESD事件时提供检测信号;以及触发单元 ，响应于检测信号顺序地接通第二NMOS晶体管和第一NMOS晶体管，使得经由第一和第二NMOS晶体管从电力线到地形成放电路径。 触发单元包括耦合在电源线和第二NMOS晶体管的栅极之间的第一PMOS晶体管，第四电阻器和第二PMOS晶体管，其具有耦合到二极管的阴极的栅极用于接收检测信号。

公开(公告)号：US09001479B2

公开(公告)日：2015-04-07

申请号：US13742854

申请日：2013-01-16

Applicant: MediaTek Inc.

Inventor： Chien-Hui Chuang

IPC: H02H9/00 ,  H01L27/02 ,  H03K19/003

CPC classification number: H01L27/0266 ,  H01L27/0277 ,  H03K19/00315

Abstract: An electrostatic discharge (ESD) protection circuit is provided. A first NMOS transistor is coupled to a power line. A second NMOS transistor is coupled between the first transistor and a ground. A detection unit provides a detection signal when an ESD event occurs at the power line. A trigger unit turns on the second NMOS transistor and the first NMOS transistor in sequence in response to the detection signal, such that a discharge path is formed from the power line to the ground via the first and second NMOS transistors.

Abstract translation: 提供静电放电（ESD）保护电路。 第一NMOS晶体管耦合到电力线。 第二NMOS晶体管耦合在第一晶体管和地之间。 当在电力线上发生ESD事件时，检测单元提供检测信号。 触发器单元响应于检测信号依次接通第二NMOS晶体管和第一NMOS晶体管，使得经由第一和第二NMOS晶体管从电力线到地形成放电路径。