公开(公告)号：US20250076950A1

公开(公告)日：2025-03-06

申请号：US18241909

申请日：2023-09-04

Applicant: MEDIATEK INC.

Inventor： Chih-Hsiang Hsiao ,  Chih-Pin Su

IPC: G06F1/28 ,  G06F1/30

Abstract: A power management system includes at least one device, at least one memory management unit (MMU), a processor, and at least one device controller, wherein the at least one MMU corresponds to the at least one device, respectively. The processor is arranged to execute at least one access control power manager, an operating system (OS), and a hypervisor, wherein the OS is arranged to generate a trigger signal, and the hypervisor is arranged to generate a first hint according to the trigger signal. The at least one device controller is arranged to control the at least one access control power manager according to the first hint, to manage at least one power of the at least one MMU.

公开(公告)号：US11556654B2

公开(公告)日：2023-01-17

申请号：US17103927

申请日：2020-11-24

Applicant: MediaTek Inc.

Inventor： Yu-Tien Chang ,  Chih-Pin Su ,  Hungwen Li

IPC: G06F21/00 ,  G06F21/57 ,  G06F21/53 ,  G06F21/79

Abstract: A system is provided to perform secure operations. The system includes an I/O subsystem, a memory subsystem and processors. The processors are operative to execute processes in trusted execution environments (TEEs) and rich execution environments (REEs). Each of the TEEs and the REEs is identified by a corresponding access identifier (AID) and protected by a corresponding system resource protection unit (SRPU). The corresponding SRPU of a TEE includes instructions, when executed by a corresponding processor, cause the corresponding processor to control access to the TEE using a data structure including allowed AIDs and pointers to memory locations accessible by the allowed AIDs.

公开(公告)号：US12061923B2

公开(公告)日：2024-08-13

申请号：US17524046

申请日：2021-11-11

Applicant: MediaTek Inc.

Inventor： Chih-Hsiang Hsiao ,  Chih-Pin Su

IPC: G06F9/455

CPC classification number: G06F9/45558 ,  G06F2009/45583

Abstract: A system includes a memory addressable by addresses within a physical address (PA) space, and one or more processors that perform operations of virtual machines (VMs). The VMs are allocated with extended PA regions outside the PA space. The system further includes a memory interface controller coupled to the memory and the one or more processors. The memory interface controller receives a request for accessing an address in the extended PA regions from a requesting VM, and uses a remap circuit to map the address in the extended PA regions to a remapped address in the PA space. A memory protection unit (MPU) in the memory interface controller grants or denies the request based on stored information indicating whether the remapped address is accessible to the requesting VM.

公开(公告)号：US20220179677A1

公开(公告)日：2022-06-09

申请号：US17524046

申请日：2021-11-11

Applicant: MediaTek Inc.

Inventor： Chih-Hsiang Hsiao ,  Chih-Pin Su

IPC: G06F9/455

Abstract: A system includes a memory addressable by addresses within a physical address (PA) space, and one or more processors that perform operations of virtual machines (VMs). The VMs are allocated with extended PA regions outside the PA space. The system further includes a memory interface controller coupled to the memory and the one or more processors. The memory interface controller receives a request for accessing an address in the extended PA regions from a requesting VM, and uses a remap circuit to map the address in the extended PA regions to a remapped address in the PA space. A memory protection unit (MPU) in the memory interface controller grants or denies the request based on stored information indicating whether the remapped address is accessible to the requesting VM.

公开(公告)号：US20210192056A1

公开(公告)日：2021-06-24

申请号：US17103927

申请日：2020-11-24

Applicant: MediaTek Inc.

Inventor： Yu-Tien Chang ,  Chih-Pin Su ,  Hungwen Li

IPC: G06F21/57 ,  G06F21/53 ,  G06F21/79

Abstract: A system is provided to perform secure operations. The system includes an I/O subsystem, a memory subsystem and processors. The processors are operative to execute processes in trusted execution environments (TEEs) and rich execution environments (REEs). Each of the TEEs and the REEs is identified by a corresponding access identifier (AID) and protected by a corresponding system resource protection unit (SRPU). The corresponding SRPU of a TEE includes instructions, when executed by a corresponding processor, cause the corresponding processor to control access to the TEE using a data structure including allowed AIDs and pointers to memory locations accessible by the allowed AIDs.

公开(公告)号：US20170060783A1

公开(公告)日：2017-03-02

申请号：US15064601

申请日：2016-03-09

Applicant: MEDIATEK INC.

Inventor： Sheng-Yu Chiu ,  Ching-Fu Kung ,  Chih-Pin Su ,  Ming-Hsien Hsieh

IPC: G06F12/14 ,  G06F12/10 ,  G06F3/06

CPC classification number: G06F12/1483 ,  G06F12/1009 ,  G06F12/145 ,  G06F2212/1052

Abstract: An apparatus for performing secure memory allocation control in an electronic device and an associated method are provided. The electronic device may include a plurality of bus master circuits, each of which has capability of accessing data through a bus of the electronic device, and may further include a plurality of master side memory address filters (MAFs) that are coupled between the bus and the bus master circuits, where the apparatus may include a control circuit that is coupled to the master side MAFs. In addition, the control circuit may be arranged for controlling secure memory allocation of the electronic device through the master side MAFs, to restrict any unauthorized access to any portion of secure data within the electronic device. Additionally, the master side MAFs may be arranged for selectively restricting data accessing activities of the bus master circuits through memory address filtering.

Abstract translation: 提供一种用于在电子设备中执行安全存储器分配控制的装置和相关联的方法。 电子设备可以包括多个总线主电路，每个总线主电路具有通过电子设备的总线访问数据的能力，并且还可以包括多个主侧存储器地址过滤器（MAF），其耦合在总线与 总线主电路，其中装置可以包括耦合到主侧MAF的控制电路。 此外，控制电路可以被布置用于通过主侧MAF来控制电子设备的安全存储器分配，以限制对电子设备内的任何安全数据部分的未经授权的访问。 此外，主侧MAF可以被布置用于通过存储器地址过滤来选择性地限制总线主控电路的数据访问活动。