公开(公告)号：US20150200565A1

公开(公告)日：2015-07-16

申请号：US14555586

申请日：2014-11-27

Applicant: MEDIATEK INC.

Inventor： Chih-Ching Lin ,  Yi-Ping Kao ,  Chun-Sung Su

IPC: H02J9/00 ,  H02J4/00

CPC classification number: G06F1/3287 ,  G06F1/3234 ,  H01L23/5286 ,  Y02D10/171 ,  Y10T307/305 ,  Y10T307/391

Abstract: The present invention provides an intergrated circuit. The intergrated circuit comprises: a plurality of core power sources; and a plurality of core power domains, coupled to the core power sources, respectively; wherein the core power domains are overlapped with each other.

Abstract translation: 本发明提供一种集成电路。 集成电路包括：多个核心电源; 以及分别耦合到所述核心电源的多个核心电源域; 其中核心功率域彼此重叠。

公开(公告)号：US10114437B2

公开(公告)日：2018-10-30

申请号：US15221919

申请日：2016-07-28

Applicant: MediaTek Inc.

Inventor： Yi-Chang Zhuang ,  Lee-Kee Yong ,  Wu-an Kuo ,  Yi-Ping Kao ,  Alice Wang ,  Uming Ko

IPC: G06F1/28 ,  H04B1/3827 ,  G06F9/4401 ,  G06F1/10

Abstract: A portable device is provided. A first processor performs an initial procedure according to an operation clock with a first frequency value and an operation voltage with a first voltage value, and performs a calibration procedure according to the operation clock with a second frequency value and the operation voltage with a second voltage value when the initial procedure has been performed and a self-calibration event is present. A second processor detects whether a specific function of the calibration procedure is being performed by the first processor. The second processor stores the second frequency value and the second voltage value into a storage unit after the calibration procedure is performed. The second voltage value is lower than the first voltage value, and the second frequency value is lower than the first frequency value.

公开(公告)号：US10048742B2

公开(公告)日：2018-08-14

申请号：US14555586

申请日：2014-11-27

Applicant: MEDIATEK INC.

Inventor： Chih-Ching Lin ,  Yi-Ping Kao ,  Chun-Sung Su

IPC: G06F1/32 ,  H01L23/528

Abstract: The present invention provides an integrated circuit. The integrated circuit comprises: a plurality of core power sources; and a plurality of core power domains, coupled to the core power sources, respectively; wherein the core power domains are overlapped with each other.