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公开(公告)号:US09690365B2
公开(公告)日:2017-06-27
申请号:US15138462
申请日:2016-04-26
Applicant: MediaTek Inc.
Inventor: Hugh Thomas Mair , Yi-Te Chiu , Che-Wei Wu , Lee-Kee Yong , Chia-Wei Wang , Cheng-Hsing Chien , Uming Ko
CPC classification number: G06F1/3296 , G06F1/3275 , Y02D10/14 , Y02D10/172
Abstract: A processing device performs dual-rail power equalization for its memory cell array and logic circuitry. The memory cell array is coupled to a first power rail through a first switch to receive a first voltage level. The logic circuitry is coupled to a second power rail through a second switch to receive a second voltage level that is different from the first voltage level. The processing device also includes a power switch coupled to at least the second power rail and operative to be enabled to equalize voltage supplied to the memory cell array and the logic circuitry.
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公开(公告)号:US20160320821A1
公开(公告)日:2016-11-03
申请号:US15138462
申请日:2016-04-26
Applicant: MediaTek Inc.
Inventor: Hugh Thomas Mair , Yi-Te Chiu , Che-Wei Wu , Lee-Kee Yong , Chia-Wei Wang , Cheng-Hsing Chien , Uming Ko
IPC: G06F1/28
CPC classification number: G06F1/3296 , G06F1/3275 , Y02D10/14 , Y02D10/172
Abstract: A processing device performs dual-rail power equalization for its memory cell array and logic circuitry. The memory cell array is coupled to a first power rail through a first switch to receive a first voltage level. The logic circuitry is coupled to a second power rail through a second switch to receive a second voltage level that is different from the first voltage level. The processing device also includes a power switch coupled to at least the second power rail and operative to be enabled to equalize voltage supplied to the memory cell array and the logic circuitry.
Abstract translation: 处理装置为其存储单元阵列和逻辑电路执行双轨功率均衡。 存储单元阵列通过第一开关耦合到第一电源轨,以接收第一电压电平。 逻辑电路通过第二开关耦合到第二电源轨,以接收不同于第一电压电平的第二电压电平。 处理装置还包括耦合到至少第二电力轨的功率开关,并且被操作以使得能够均衡提供给存储单元阵列和逻辑电路的电压。
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公开(公告)号:US10114437B2
公开(公告)日:2018-10-30
申请号:US15221919
申请日:2016-07-28
Applicant: MediaTek Inc.
Inventor: Yi-Chang Zhuang , Lee-Kee Yong , Wu-an Kuo , Yi-Ping Kao , Alice Wang , Uming Ko
IPC: G06F1/28 , H04B1/3827 , G06F9/4401 , G06F1/10
Abstract: A portable device is provided. A first processor performs an initial procedure according to an operation clock with a first frequency value and an operation voltage with a first voltage value, and performs a calibration procedure according to the operation clock with a second frequency value and the operation voltage with a second voltage value when the initial procedure has been performed and a self-calibration event is present. A second processor detects whether a specific function of the calibration procedure is being performed by the first processor. The second processor stores the second frequency value and the second voltage value into a storage unit after the calibration procedure is performed. The second voltage value is lower than the first voltage value, and the second frequency value is lower than the first frequency value.
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