公开(公告)号：US10659794B2

公开(公告)日：2020-05-19

申请号：US16293647

申请日：2019-03-06

申请人： MEDIATEK INC.

发明人： Chi-Min Chen ,  Min-Hao Chiu ,  Chia-Yun Cheng ,  Yung-Chang Chang

IPC分类号： H04N19/124 ,  H04N19/186 ,  H04N19/182 ,  H04N19/91 ,  H04N19/157 ,  H04N19/44 ,  H04N19/119

摘要： A palette decoding apparatus includes a palette color storage device which stores palette colors, a color index storage device which stores color indices of pixels, and a palette value processing circuit which generates a palette value for each pixel by reading data from the color index storage device and the palette color storage device. A frame is divided into first coding units, and each first coding unit is sub-divided into one or more second coding units. Before a palette value of a last pixel in a first coding unit is generated by the palette value processing circuit, a palette value of a non-last pixel in the first coding unit is generated by the palette value processing circuit and used by a reconstruction circuit of the video decoder.

公开(公告)号：US20190123833A1

公开(公告)日：2019-04-25

申请号：US16163581

申请日：2018-10-18

申请人： MEDIATEK INC.

发明人： Min-Hao Chiu ,  Chia-Yun Cheng ,  Yung-Chang Chang

IPC分类号： H04B10/69 ,  G06T9/00 ,  H04N19/70 ,  H04N19/184

摘要： A decoding apparatus is used for decoding region of interest (ROI) regions in an image, and includes a storage device, a pre-processing circuit, a decoding circuit, and an information fetching circuit. The pre-processing circuit performs a syntax pre-parsing operation upon a bitstream to obtain necessary information of the ROI regions, and stores the necessary information into the storage device. The decoding circuit performs a decoding operation upon the bitstream to decode the ROI regions, wherein the decoding operation includes syntax parsing of the bitstream. The information fetching circuit reads and analyzes the necessary information, and delivers at least a portion of the necessary information to the decoding circuit. A processing time of obtaining necessary information of one ROI region at the pre-processing circuit overlaps a processing time of decoding another ROI region at the decoding circuit.

公开(公告)号：US10257524B2

公开(公告)日：2019-04-09

申请号：US15197741

申请日：2016-06-29

申请人： MEDIATEK INC.

发明人： Min-Hao Chiu ,  Yung-Chang Chang

IPC分类号： H04N19/18 ,  H04N19/50 ,  H04N19/426 ,  H04N19/436

摘要： A residual up-sampling apparatus has a residual up-sampling buffer and a shared residual up-sampling circuit. The residual up-sampling buffer stores an intermediate residual up-sampling result. The shared residual up-sampling circuit employs a same processing kernel to perform a first-direction residual up-sampling operation and a second-direction residual up-sampling operation. The first-direction residual up-sampling operation processes an inverse transform output of an inverse transform circuit to generate the intermediate residual up-sampling result to the residual up-sampling buffer. The second-direction residual up-sampling operation performs transpose access upon the residual up-sampling buffer to retrieve the intermediate residual up-sampling result, and processes the intermediate residual up-sampling result to generate a final residual up-sampling result.

公开(公告)号：US10104397B2

公开(公告)日：2018-10-16

申请号：US14716904

申请日：2015-05-20

申请人： MEDIATEK INC.

发明人： Meng-Jye Hu ,  Yung-Chang Chang ,  Chia-Yun Cheng

IPC分类号： H04N19/593 ,  H04N19/51 ,  H04N19/55 ,  H04N19/563 ,  H04N19/44 ,  H04N19/423

摘要： A video processing apparatus includes a reconstruct circuit, a storage device, and an intra prediction circuit. The reconstruct circuit generates reconstructed pixels of a first block of a picture. The storage device at least stores a portion of the reconstructed pixels of the first block, wherein a capacity of the storage device is smaller than a reconstructed data size of the picture. The intra prediction circuit performs intra prediction of a second block of the picture based at least partly on pixel data obtained from the storage device.

公开(公告)号：US20180295380A1

公开(公告)日：2018-10-11

申请号：US15832959

申请日：2017-12-06

申请人： MEDIATEK INC.

发明人： Min-Hao Chiu ,  Chia-yun Cheng ,  Yung-Chang Chang

IPC分类号： H04N19/513 ,  H04N19/55

CPC分类号： H04N19/521 ,  H04N19/52 ,  H04N19/55 ,  H04N19/573

摘要： A method and apparatus for video encoding or decoding used by an AVS2 (Second Generation of Audio Video Coding Standard) video encoder or decoder respectively are disclosed. According to this method, first motion vectors associated with spatial neighboring blocks of a current block are determined. For each spatial neighboring block, a value of 1 is assigned to a first BlockDistance associated with the spatial neighboring block if a corresponding first reference picture is a G picture or GB picture. Motion vector predictor candidates are derived from the first motion vectors by scaling each first motion vector according to a corresponding first BlockDistance and a current BlockDistance. A final motion vector predictor is determined among the motion vector predictor candidates. The current motion vector is encoded or decoded using the final motion vector predictor

公开(公告)号：US10075722B1

公开(公告)日：2018-09-11

申请号：US14537850

申请日：2014-11-10

申请人： MEDIATEK INC.

发明人： Chia-Yun Cheng ,  Shun-Hsiang Chuang ,  Yung-Chang Chang

IPC分类号： H04N19/44 ,  H04N7/12 ,  H04J3/06 ,  H04N7/18 ,  H04N11/02

CPC分类号： H04N19/436 ,  H04N19/423

摘要： A multi-core video decoder system includes a plurality of video decoder cores and a storage device. The video decoder cores are used to decode a picture, wherein each of the video decoder cores decodes a portion of the picture. The storage device has at least one shared storage space accessed by different video decoder cores of the video decoder cores. In addition, an associated video decoding method includes: performing a plurality of video decoding operations to decode a picture, wherein each of the video decoding operations decodes a portion of the picture; and controlling different video decoding operations of the video decoding operations to access at least one shared storage space.

公开(公告)号：US20180139464A1

公开(公告)日：2018-05-17

申请号：US15803388

申请日：2017-11-03

申请人： MEDIATEK INC.

发明人： Min-Hao CHIU ,  Ping Chao ,  Chia-Hung Kao ,  Huei-Min Lin ,  Hsiu-Yi Lin ,  Chi-Hung Chen ,  Chia-Yun Cheng ,  Chih-Ming Wang ,  Yung-Chang Chang

IPC分类号： H04N19/44 ,  H04N19/423 ,  H04N19/172

摘要： Aspects of the disclosure provide a video decoding system. The video decoding system can include a decoder core configured to selectively decode independently decodable tiles in a picture, each tile including largest coding units (LCUs) each associated with a pair of picture-based (X, Y) coordinates or tile-based (X, Y) coordinates, and memory management circuitry configured to translate one or two coordinates of a current LCU to generate one or two translated coordinates, and to determine a target memory space storing reference data for decoding the current LCU based on the one or two translated coordinates.

公开(公告)号：US09894382B2

公开(公告)日：2018-02-13

申请号：US14753004

申请日：2015-06-28

申请人： MEDIATEK INC.

发明人： Shun-Hsiang Chuang ,  Chih-Ming Wang ,  Yung-Chang Chang

IPC分类号： H04N7/12 ,  H04N19/593 ,  H04N19/52 ,  H04N19/176 ,  H04N19/119

CPC分类号： H04N19/593 ,  H04N19/119 ,  H04N19/176 ,  H04N19/52

摘要： A motion vector predictor determination method includes: checking if motion vector data of at least one first neighbor unit adjacent to a block and motion vector data of at least one second neighbor unit adjacent to the block are identical to each other; and when a checking result indicates that the motion vector data of the at least one first neighbor unit is identical to the motion vector data of the at least one second neighbor unit, assigning a motion vector predictor determined for a first sub-block within the block to a second sub-block within the block. The motion vector data of the at least one first neighbor unit is involved in determining the motion vector predictor of the first sub-block, and the motion vector data of the at least one second neighbor unit is not involved in determining the motion vector predictor of the first sub-block.

公开(公告)号：US09888251B2

公开(公告)日：2018-02-06

申请号：US15208626

申请日：2016-07-13

申请人： MEDIATEK INC.

发明人： Yung-Chang Chang

IPC分类号： H04N19/186 ,  H04N19/105 ,  H04N19/117 ,  H04N19/132 ,  H04N19/139 ,  H04N19/182 ,  H04N19/44 ,  H04N19/86

CPC分类号： H04N19/186 ,  H04N19/105 ,  H04N19/117 ,  H04N19/132 ,  H04N19/139 ,  H04N19/182 ,  H04N19/44 ,  H04N19/86

摘要： A video processing apparatus includes a control unit, a storage device, a video decoder and a video processor. The control unit is arranged for generating a color depth control signal. The video decoder is coupled to the storage device and the control unit, and arranged for referring to the color depth control signal to enable a target video decoding mode selected from a plurality of supported video decoding modes respectively corresponding to different output color depths, and decoding an encoded video bitstream under the target video decoding mode to generate decoded video pictures (sequence) to the storage device. The video processor is coupled to at least the storage device, and arranged for processing picture data derived from the data buffered in the storage device to generate output video pictures (sequence) to a display apparatus.

公开(公告)号：US20180020221A1

公开(公告)日：2018-01-18

申请号：US15641224

申请日：2017-07-04

申请人： MEDIATEK INC.

发明人： Ming-Long Wu ,  Tung-Hsing Wu ,  Li-Heng Chen ,  Ting-An Lin ,  Yi-Hsin Huang ,  Chung-Hua Tsai ,  Chia-Yun Cheng ,  Han-Liang Chou ,  Yung-Chang Chang

IPC分类号： H04N19/13 ,  H04N21/2665 ,  H04N21/2365 ,  H04N21/2343 ,  H04N19/70 ,  H04N19/44 ,  H04N19/172 ,  H04N21/845 ,  H04N19/124

CPC分类号： H04N19/13 ,  H04N19/124 ,  H04N19/172 ,  H04N19/174 ,  H04N19/18 ,  H04N19/44 ,  H04N19/70 ,  H04N21/234363 ,  H04N21/2365 ,  H04N21/2665 ,  H04N21/8456

摘要： A video encoder has a processing circuit and a universal binary entropy (UBE) syntax encoder. The processing circuit processes pixel data of a video frame to generate encoding-related data, wherein the encoding-related data comprise at least quantized transform coefficients. The UBE syntax encoder processes a plurality of syntax elements to generate UBE syntax data. The encoding-related data are represented by the syntax elements. The processing circuit operates according to a video coding standard. The video coding standard supports arithmetic encoding. The UBE syntax data contain no arithmetic-encoded syntax data.