公开(公告)号：US20180020221A1

公开(公告)日：2018-01-18

申请号：US15641224

申请日：2017-07-04

申请人： MEDIATEK INC.

发明人： Ming-Long Wu ,  Tung-Hsing Wu ,  Li-Heng Chen ,  Ting-An Lin ,  Yi-Hsin Huang ,  Chung-Hua Tsai ,  Chia-Yun Cheng ,  Han-Liang Chou ,  Yung-Chang Chang

IPC分类号： H04N19/13 ,  H04N21/2665 ,  H04N21/2365 ,  H04N21/2343 ,  H04N19/70 ,  H04N19/44 ,  H04N19/172 ,  H04N21/845 ,  H04N19/124

CPC分类号： H04N19/13 ,  H04N19/124 ,  H04N19/172 ,  H04N19/174 ,  H04N19/18 ,  H04N19/44 ,  H04N19/70 ,  H04N21/234363 ,  H04N21/2365 ,  H04N21/2665 ,  H04N21/8456

摘要： A video encoder has a processing circuit and a universal binary entropy (UBE) syntax encoder. The processing circuit processes pixel data of a video frame to generate encoding-related data, wherein the encoding-related data comprise at least quantized transform coefficients. The UBE syntax encoder processes a plurality of syntax elements to generate UBE syntax data. The encoding-related data are represented by the syntax elements. The processing circuit operates according to a video coding standard. The video coding standard supports arithmetic encoding. The UBE syntax data contain no arithmetic-encoded syntax data.

公开(公告)号：US10904577B2

公开(公告)日：2021-01-26

申请号：US16194396

申请日：2018-11-19

申请人： MEDIATEK INC.

发明人： Li-Heng Chen ,  Chung-Hua Tsai ,  Tung-Hsing Wu ,  Lien-Fei Chen ,  Yu-Kun Lin ,  Yi-Hsin Huang ,  Han-Liang Chou

IPC分类号： H04N19/184 ,  H04N19/85 ,  H04N19/70

摘要： A video compression system includes a video encoder and a bitstream processing circuit. The video encoder is hardware that performs hardware video encoding upon frames to generate a first bitstream. The first bitstream is output from an entropy encoding circuit of the video encoder. The bitstream processing circuit performs a bitstream post-processing operation upon the first bitstream to produce a second bitstream that is different from the first bitstream, and outputs the second bitstream as a compression output of the frames.

公开(公告)号：US20180027240A1

公开(公告)日：2018-01-25

申请号：US15653550

申请日：2017-07-19

申请人： MEDIATEK INC.

发明人： Yen-Chao Huang ,  Li-Heng Chen ,  Tung-Hsing Wu ,  Chung-Hua Tsai ,  Lien-Fei Chen ,  Han-Liang Chou

IPC分类号： H04N19/159 ,  H04N19/50 ,  H04N19/176 ,  H04N19/61

CPC分类号： H04N19/159 ,  H04N19/174 ,  H04N19/176 ,  H04N19/436 ,  H04N19/50 ,  H04N19/61 ,  H04N19/91

摘要： A video encoding apparatus has a bitstream buffer and a first video encoder. The first video encoder sequentially encodes coding blocks of a first video frame segment in a first encoding order, and outputs encoded data of the coding blocks of the first video frame segment to the bitstream buffer. The first video frame segment is partitioned into a plurality of column tiles, each having at least one tile. The first encoding order is identical to an encoding order of encoding a video frame segment with only a single column tile.

公开(公告)号：US10412390B2

公开(公告)日：2019-09-10

申请号：US15641224

申请日：2017-07-04

申请人： MEDIATEK INC.

发明人： Ming-Long Wu ,  Tung-Hsing Wu ,  Li-Heng Chen ,  Ting-An Lin ,  Yi-Hsin Huang ,  Chung-Hua Tsai ,  Chia-Yun Cheng ,  Han-Liang Chou ,  Yung-Chang Chang

IPC分类号： H04N19/13 ,  H04N19/70 ,  H04N19/44 ,  H04N21/23 ,  H04N21/84 ,  H04N19/124 ,  H04N19/172 ,  H04N19/18 ,  H04N19/174 ,  H04N21/2365 ,  H04N21/2665 ,  H04N21/2343 ,  H04N21/845

摘要： A video encoder has a processing circuit and a universal binary entropy (UBE) syntax encoder. The processing circuit processes pixel data of a video frame to generate encoding-related data, wherein the encoding-related data comprise at least quantized transform coefficients. The UBE syntax encoder processes a plurality of syntax elements to generate UBE syntax data. The encoding-related data are represented by the syntax elements. The processing circuit operates according to a video coding standard. The video coding standard supports arithmetic encoding. The UBE syntax data contain no arithmetic-encoded syntax data.

公开(公告)号：US20190246144A1

公开(公告)日：2019-08-08

申请号：US16194396

申请日：2018-11-19

申请人： MEDIATEK INC.

发明人： Li-Heng Chen ,  Chung-Hua Tsai ,  Tung-Hsing Wu ,  Lien-Fei Chen ,  Yu-Kun Lin ,  Yi-Hsin Huang ,  Han-Liang Chou

IPC分类号： H04N19/85 ,  H04N19/70 ,  H04N19/184

CPC分类号： H04N19/85 ,  H04N19/184 ,  H04N19/70

摘要： A video compression system includes a video encoder and a bitstream processing circuit. The video encoder is hardware that performs hardware video encoding upon frames to generate a first bitstream. The first bitstream is output from an entropy encoding circuit of the video encoder. The bitstream processing circuit performs a bitstream post-processing operation upon the first bitstream to produce a second bitstream that is different from the first bitstream, and outputs the second bitstream as a compression output of the frames.