公开(公告)号：US20130264681A1

公开(公告)日：2013-10-10

申请号：US13907981

申请日：2013-06-03

Applicant: MEDIATEK INC.

Inventor： Chao-Chun Tu ,  Shih-Hung Lin ,  Chih-Chien Huang ,  Tien-Chang Chang

IPC: H01L23/538

CPC classification number: H01L23/00 ,  H01L21/00 ,  H01L23/5223 ,  H01L23/5286 ,  H01L23/5384 ,  H01L27/00 ,  H01L28/00 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit chip includes a semiconductor substrate; a first interconnection wire having a first portion and a second portion on the semiconductor substrate, wherein the second portion is separated from the first portion; a second interconnection wire situated under the first interconnection wire; a first conductive via electrically coupling the first portion with the second interconnection wire; a conductive layer situated between the first interconnection wire and the second interconnection wire; and a second conductive via electrically coupling the conductive layer with the second portion.

Abstract translation: 集成电路芯片包括半导体衬底; 第一互连线，其具有在所述半导体衬底上的第一部分和第二部分，其中所述第二部分与所述第一部分分离; 位于所述第一互连线下方的第二互连线; 第一导电通孔，电连接第一部分与第二互连线; 位于第一互连线和第二互连线之间的导电层; 以及将导电层与第二部分电耦合的第二导电通孔。

公开(公告)号：US08766417B2

公开(公告)日：2014-07-01

申请号：US13907981

申请日：2013-06-03

Applicant: Mediatek Inc.

Inventor： Chao-Chun Tu ,  Shih-Hung Lin ,  Chih-Chien Huang ,  Tien-Chang Chang

IPC: H01L23/495 ,  H01L23/00 ,  H01L49/02 ,  H01L27/00 ,  H01L21/00

CPC classification number: H01L23/00 ,  H01L21/00 ,  H01L23/5223 ,  H01L23/5286 ,  H01L23/5384 ,  H01L27/00 ,  H01L28/00 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit chip includes a semiconductor substrate; a first interconnection wire having a first portion and a second portion on the semiconductor substrate, wherein the second portion is separated from the first portion; a second interconnection wire situated under the first interconnection wire; a first conductive via electrically coupling the first portion with the second interconnection wire; a conductive layer situated between the first interconnection wire and the second interconnection wire; and a second conductive via electrically coupling the conductive layer with the second portion.

Abstract translation: 集成电路芯片包括半导体衬底; 第一互连线，其具有在所述半导体衬底上的第一部分和第二部分，其中所述第二部分与所述第一部分分离; 位于所述第一互连线下方的第二互连线; 第一导电通孔，电连接第一部分与第二互连线; 位于第一互连线和第二互连线之间的导电层; 以及将导电层与第二部分电耦合的第二导电通孔。