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12 条记录 (耗时 0.012 秒)

    INTEGRATED CIRCUIT CHIP WITH REDUCED IR DROP
    1.
    发明申请
    INTEGRATED CIRCUIT CHIP WITH REDUCED IR DROP 有权
    集成电路芯片，减少红外线

    公开(公告)号：US20130264681A1

    公开(公告)日：2013-10-10

    申请号：US13907981

    申请日：2013-06-03

    申请人： MEDIATEK INC.

    发明人： Chao-Chun Tu ,  Shih-Hung Lin ,  Chih-Chien Huang ,  Tien-Chang Chang

    IPC分类号： H01L23/538

    CPC分类号： H01L23/00 ,  H01L21/00 ,  H01L23/5223 ,  H01L23/5286 ,  H01L23/5384 ,  H01L27/00 ,  H01L28/00 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An integrated circuit chip includes a semiconductor substrate; a first interconnection wire having a first portion and a second portion on the semiconductor substrate, wherein the second portion is separated from the first portion; a second interconnection wire situated under the first interconnection wire; a first conductive via electrically coupling the first portion with the second interconnection wire; a conductive layer situated between the first interconnection wire and the second interconnection wire; and a second conductive via electrically coupling the conductive layer with the second portion.

    摘要翻译： 集成电路芯片包括半导体衬底; 第一互连线，其具有在所述半导体衬底上的第一部分和第二部分，其中所述第二部分与所述第一部分分离; 位于所述第一互连线下方的第二互连线; 第一导电通孔，电连接第一部分与第二互连线; 位于第一互连线和第二互连线之间的导电层; 以及将导电层与第二部分电耦合的第二导电通孔。

    METHOD FOR INCLUDING DECOUPLING CAPACITORS INTO SEMICONDUCTOR CIRCUIT HAVING LOGIC CIRCUIT THEREIN AND SEMICONDUCTOR CIRCUIT THEREOF
    2.
    发明申请
    METHOD FOR INCLUDING DECOUPLING CAPACITORS INTO SEMICONDUCTOR CIRCUIT HAVING LOGIC CIRCUIT THEREIN AND SEMICONDUCTOR CIRCUIT THEREOF 审中-公开
    将解耦电容器放入具有逻辑电路的半导体电路及其半导体电路的方法

    公开(公告)号：US20140175608A1

    公开(公告)日：2014-06-26

    申请号：US14190058

    申请日：2014-02-25

    申请人： MEDIATEK INC.

    发明人： Tien-Chang Chang ,  Ming-Tzong Yang ,  Tao Cheng ,  Cheng-Hsing Chien ,  Hsin-Hsin Hsiao

    IPC分类号： H01L49/02

    CPC分类号： H01L28/40 ,  H01L27/0629 ,  H01L27/0811

    摘要： A method for including decoupling capacitors into a semiconductor circuit having at least a logic circuit therein, includes: arranging a first decoupling capacitor and a second decoupling capacitor into a first area and a second area around the logic circuit respectively, wherein a gate oxide thickness of the first decoupling capacitor is different from a gate oxide thickness of the second decoupling capacitor, and a distance between the first area and the first logic circuit is shorter than a distance between the second area and the second logic circuit.

    摘要翻译： 一种用于将去耦电容器包括至其中至少具有逻辑电路的半导体电路的方法包括：将第一去耦电容器和第二去耦电容器分别布置在逻辑电路周围的第一区域和第二区域中，其中栅极氧化物厚度 第一去耦电容器与第二去耦电容器的栅极氧化物厚度不同，并且第一区域和第一逻辑电路之间的距离小于第二区域和第二逻辑电路之间的距离。

    Integrated circuit chip with reduced IR drop
    6.
    发明授权
    Integrated circuit chip with reduced IR drop 有权
    集成电路芯片具有降低的IR降

    公开(公告)号：US08766417B2

    公开(公告)日：2014-07-01

    申请号：US13907981

    申请日：2013-06-03

    申请人： Mediatek Inc.

    发明人： Chao-Chun Tu ,  Shih-Hung Lin ,  Chih-Chien Huang ,  Tien-Chang Chang

    IPC分类号： H01L23/495 ,  H01L23/00 ,  H01L49/02 ,  H01L27/00 ,  H01L21/00

    CPC分类号： H01L23/00 ,  H01L21/00 ,  H01L23/5223 ,  H01L23/5286 ,  H01L23/5384 ,  H01L27/00 ,  H01L28/00 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An integrated circuit chip includes a semiconductor substrate; a first interconnection wire having a first portion and a second portion on the semiconductor substrate, wherein the second portion is separated from the first portion; a second interconnection wire situated under the first interconnection wire; a first conductive via electrically coupling the first portion with the second interconnection wire; a conductive layer situated between the first interconnection wire and the second interconnection wire; and a second conductive via electrically coupling the conductive layer with the second portion.

    摘要翻译： 集成电路芯片包括半导体衬底; 第一互连线，其具有在所述半导体衬底上的第一部分和第二部分，其中所述第二部分与所述第一部分分离; 位于所述第一互连线下方的第二互连线; 第一导电通孔，电连接第一部分与第二互连线; 位于第一互连线和第二互连线之间的导电层; 以及将导电层与第二部分电耦合的第二导电通孔。

    SEMICONDUCTOR PACKAGE WITH IMPROVED RELIABILITY
    10.
    发明申请
    SEMICONDUCTOR PACKAGE WITH IMPROVED RELIABILITY 有权

    公开(公告)号：US20220181228A1

    公开(公告)日：2022-06-09

    申请号：US17512665

    申请日：2021-10-27

    申请人： MEDIATEK INC.

    发明人： Tien-Chang Chang ,  Yan-Liang Ji

    IPC分类号： H01L23/31 ,  H01L23/498 ,  H01L23/00

    摘要： A semiconductor device includes a semiconductor die having an active surface, an opposite surface, a vertical sidewall extending between the active surface and the opposite surface, and input/output (I/O) connections disposed on the active surface. A redistribution layer (RDL) is disposed on the active surface of the semiconductor die. A plurality of first connecting elements is disposed on the RDL. A molding compound encapsulates the opposite surface and the vertical sidewall of the semiconductor die. The molding compound also covers the RDL and surrounds the plurality of first connecting elements. An interconnect substrate is mounted on the plurality of first connecting elements and on the molding compound.