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公开(公告)号：US09064938B2
公开(公告)日：2015-06-23
申请号：US13905275
申请日：2013-05-30
IPC分类号： H01L21/768 , H01L23/535 , H01L27/02
CPC分类号： H01L21/76895 , H01L27/0296 , H01L2224/05554
摘要： An integrated circuit including an ESD network including a portion located in ESD subareas of a plurality of I/O cells where the ESD subareas are arranged in a row traversing the plurality of I/O cells. The ESD network includes ESD clamp cells and ESD trigger circuit cells wherein a portion of the network is located in the row. In some examples, the row includes an ESD trigger circuit cell with a portion in one subarea of one ESD subarea of one I/O cell and a second portion in a second ESD subarea of another I/O cell. Also described herein is a method for producing an integrated circuit layout with an ESD network.
摘要翻译： 一种包括ESD网络的集成电路，其包括位于多个I / O单元的ESD子区域中的部分，其中ESD子区域布置成穿过多个I / O单元的行。 ESD网络包括ESD钳位单元和ESD触发电路单元，其中网络的一部分位于该行中。 在一些示例中，行包括ESD触发电路单元，其具有一个I / O单元的一个ESD子区域的一个子区域中的一部分，以及另一个I / O单元的第二ESD子区域中的第二部分。 本文还描述了一种用于产生具有ESD网络的集成电路布局的方法。
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公开(公告)号：US09478529B2
公开(公告)日：2016-10-25
申请号：US14289083
申请日：2014-05-28
申请人： James W. Miller , Melanie Etherton , Alex P. Gerdemann , Mohamed S. Moosa , Jonathan M. Phillippe , Robert S. Ruth
发明人： James W. Miller , Melanie Etherton , Alex P. Gerdemann , Mohamed S. Moosa , Jonathan M. Phillippe , Robert S. Ruth
CPC分类号： H01L27/0248 , H01L24/06 , H01L27/0292 , H01L27/0296 , H02H3/20 , H02H9/04 , H02H9/046 , H05K9/006
摘要： An integrated circuit includes a plurality of I/O cells, each including a portion of the first power bus, a portion of the second power bus, and an I/O pad coupled between the portions of the first and second power buses. A first set of the plurality of I/O cells is arranged along a die edge of the integrated circuit. A second set of the plurality of I/O cells is arranged along the die edge between the first set and the die edge. For each I/O cell in the first set, the portion of the first power bus is physically connected to the portion of the first power bus of an abutting I/O cell of the second set at a boundary between the I/O cell of the first set and the abutting I/O cell of the second set. The integrated circuit includes an ESD clamp and a trigger circuit.
摘要翻译： 集成电路包括多个I / O单元，每个I / O单元包括第一电力总线的一部分，第二电力总线的一部分以及耦合在第一和第二电力总线的部分之间的I / O焊盘。 多个I / O单元的第一组沿着集成电路的管芯边缘布置。 多个I / O单元的第二组沿着模具边缘布置在第一组和模具边缘之间。 对于第一组中的每个I / O单元，第一功率总线的部分物理地连接到第二组的I / O单元之间的边界处的第二组的邻接I / O单元的第一功率总线的部分 第一组和第二组的邻接I / O单元。 集成电路包括ESD钳位和触发电路。
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公开(公告)号：US20150349522A1
公开(公告)日：2015-12-03
申请号：US14289083
申请日：2014-05-28
申请人： James W. Miller , Melanie Etherton , Alex P. Gerdemann , Mohamed S. Moosa , Jonathan M. Phillippe , Robert S. Ruth
发明人： James W. Miller , Melanie Etherton , Alex P. Gerdemann , Mohamed S. Moosa , Jonathan M. Phillippe , Robert S. Ruth
IPC分类号： H02H9/04
CPC分类号： H01L27/0248 , H01L24/06 , H01L27/0292 , H01L27/0296 , H02H3/20 , H02H9/04 , H02H9/046 , H05K9/006
摘要： An integrated circuit includes a plurality of I/O cells, each including a portion of the first power bus, a portion of the second power bus, and an I/O pad coupled between the portions of the first and second power buses. A first set of the plurality of I/O cells is arranged along a die edge of the integrated circuit. A second set of the plurality of I/O cells is arranged along the die edge between the first set and the die edge. For each I/O cell in the first set, the portion of the first power bus is physically connected to the portion of the first power bus of an abutting I/O cell of the second set at a boundary between the I/O cell of the first set and the abutting I/O cell of the second set. The integrated circuit includes an ESD clamp and a trigger circuit.
摘要翻译： 集成电路包括多个I / O单元，每个I / O单元包括第一电力总线的一部分，第二电力总线的一部分以及耦合在第一和第二电力总线的部分之间的I / O焊盘。 多个I / O单元的第一组沿着集成电路的管芯边缘布置。 多个I / O单元的第二组沿着模具边缘布置在第一组和模具边缘之间。 对于第一组中的每个I / O单元，第一功率总线的部分物理连接到第二组的I / O单元之间的边界处的第二组的邻接I / O单元的第一功率总线的部分 第一组和第二组的邻接I / O单元。 集成电路包括ESD钳位和触发电路。
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