-
公开(公告)号：US09064938B2
公开(公告)日：2015-06-23
申请号：US13905275
申请日：2013-05-30
IPC分类号： H01L21/768 , H01L23/535 , H01L27/02
CPC分类号： H01L21/76895 , H01L27/0296 , H01L2224/05554
摘要： An integrated circuit including an ESD network including a portion located in ESD subareas of a plurality of I/O cells where the ESD subareas are arranged in a row traversing the plurality of I/O cells. The ESD network includes ESD clamp cells and ESD trigger circuit cells wherein a portion of the network is located in the row. In some examples, the row includes an ESD trigger circuit cell with a portion in one subarea of one ESD subarea of one I/O cell and a second portion in a second ESD subarea of another I/O cell. Also described herein is a method for producing an integrated circuit layout with an ESD network.
摘要翻译： 一种包括ESD网络的集成电路，其包括位于多个I / O单元的ESD子区域中的部分，其中ESD子区域布置成穿过多个I / O单元的行。 ESD网络包括ESD钳位单元和ESD触发电路单元，其中网络的一部分位于该行中。 在一些示例中，行包括ESD触发电路单元，其具有一个I / O单元的一个ESD子区域的一个子区域中的一部分，以及另一个I / O单元的第二ESD子区域中的第二部分。 本文还描述了一种用于产生具有ESD网络的集成电路布局的方法。
-
公开(公告)号：US09478529B2
公开(公告)日：2016-10-25
申请号：US14289083
申请日：2014-05-28
申请人： James W. Miller , Melanie Etherton , Alex P. Gerdemann , Mohamed S. Moosa , Jonathan M. Phillippe , Robert S. Ruth
发明人： James W. Miller , Melanie Etherton , Alex P. Gerdemann , Mohamed S. Moosa , Jonathan M. Phillippe , Robert S. Ruth
CPC分类号： H01L27/0248 , H01L24/06 , H01L27/0292 , H01L27/0296 , H02H3/20 , H02H9/04 , H02H9/046 , H05K9/006
摘要： An integrated circuit includes a plurality of I/O cells, each including a portion of the first power bus, a portion of the second power bus, and an I/O pad coupled between the portions of the first and second power buses. A first set of the plurality of I/O cells is arranged along a die edge of the integrated circuit. A second set of the plurality of I/O cells is arranged along the die edge between the first set and the die edge. For each I/O cell in the first set, the portion of the first power bus is physically connected to the portion of the first power bus of an abutting I/O cell of the second set at a boundary between the I/O cell of the first set and the abutting I/O cell of the second set. The integrated circuit includes an ESD clamp and a trigger circuit.
摘要翻译： 集成电路包括多个I / O单元，每个I / O单元包括第一电力总线的一部分，第二电力总线的一部分以及耦合在第一和第二电力总线的部分之间的I / O焊盘。 多个I / O单元的第一组沿着集成电路的管芯边缘布置。 多个I / O单元的第二组沿着模具边缘布置在第一组和模具边缘之间。 对于第一组中的每个I / O单元，第一功率总线的部分物理地连接到第二组的I / O单元之间的边界处的第二组的邻接I / O单元的第一功率总线的部分 第一组和第二组的邻接I / O单元。 集成电路包括ESD钳位和触发电路。
-
公开(公告)号：US20150349522A1
公开(公告)日：2015-12-03
申请号：US14289083
申请日：2014-05-28
申请人： James W. Miller , Melanie Etherton , Alex P. Gerdemann , Mohamed S. Moosa , Jonathan M. Phillippe , Robert S. Ruth
发明人： James W. Miller , Melanie Etherton , Alex P. Gerdemann , Mohamed S. Moosa , Jonathan M. Phillippe , Robert S. Ruth
IPC分类号： H02H9/04
CPC分类号： H01L27/0248 , H01L24/06 , H01L27/0292 , H01L27/0296 , H02H3/20 , H02H9/04 , H02H9/046 , H05K9/006
摘要： An integrated circuit includes a plurality of I/O cells, each including a portion of the first power bus, a portion of the second power bus, and an I/O pad coupled between the portions of the first and second power buses. A first set of the plurality of I/O cells is arranged along a die edge of the integrated circuit. A second set of the plurality of I/O cells is arranged along the die edge between the first set and the die edge. For each I/O cell in the first set, the portion of the first power bus is physically connected to the portion of the first power bus of an abutting I/O cell of the second set at a boundary between the I/O cell of the first set and the abutting I/O cell of the second set. The integrated circuit includes an ESD clamp and a trigger circuit.
摘要翻译： 集成电路包括多个I / O单元，每个I / O单元包括第一电力总线的一部分，第二电力总线的一部分以及耦合在第一和第二电力总线的部分之间的I / O焊盘。 多个I / O单元的第一组沿着集成电路的管芯边缘布置。 多个I / O单元的第二组沿着模具边缘布置在第一组和模具边缘之间。 对于第一组中的每个I / O单元，第一功率总线的部分物理连接到第二组的I / O单元之间的边界处的第二组的邻接I / O单元的第一功率总线的部分 第一组和第二组的邻接I / O单元。 集成电路包括ESD钳位和触发电路。
-
4.发明授权Distributed electrostatic discharge protection circuit with varying clamp size 有权具有不同钳位尺寸的分布式静电放电保护电路公开(公告)号：US07589945B2
公开(公告)日：2009-09-15
申请号：US11513638
申请日：2006-08-31
IPC分类号： H02H9/00
CPC分类号： H02H9/046 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit includes a first I/O cell disposed at a substrate, the first I/O cell including a first electrostatic discharge (ESD) clamp transistor device. The first ESD clamp transistor device includes a control electrode, a first current electrode coupled to a first voltage reference bus, and second current electrode coupled to a second voltage reference bus. The first ESD clamp transistor device has a first channel width. The integrated circuit further includes a second I/O cell including a second ESD clamp transistor device. The second ESD clamp transistor device includes a control electrode, a first current electrode coupled to the first voltage reference bus, and second current electrode coupled to the second voltage reference bus. The second ESD clamp transistor device has a second channel width different than the first channel width.
摘要翻译： 集成电路包括设置在基板上的第一I / O单元，第一I / O单元包括第一静电放电（ESD）钳位晶体管器件。 第一ESD钳位晶体管器件包括控制电极，耦合到第一电压参考总线的第一电流电极和耦合到第二电压参考总线的第二电流电极。 第一ESD钳位晶体管器件具有第一通道宽度。 集成电路还包括具有第二ESD钳位晶体管器件的第二I / O单元。 第二ESD钳位晶体管器件包括控制电极，耦合到第一电压参考总线的第一电流电极和耦合到第二电压参考总线的第二电流电极。 第二ESD钳位晶体管器件具有与第一通道宽度不同的第二通道宽度。
-
5.发明申请Distributed electrostatic discharge protection circuit with varying clamp size 有权具有不同钳位尺寸的分布式静电放电保护电路公开(公告)号：US20080062596A1
公开(公告)日：2008-03-13
申请号：US11513638
申请日：2006-08-31
IPC分类号： H02H9/00
CPC分类号： H02H9/046 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit includes a first I/O cell disposed at a substrate, the first I/O cell including a first electrostatic discharge (ESD) clamp transistor device. The first ESD clamp transistor device includes a control electrode, a first current electrode coupled to a first voltage reference bus, and second current electrode coupled to a second voltage reference bus. The first ESD clamp transistor device has a first channel width. The integrated circuit further includes a second I/O cell including a second ESD clamp transistor device. The second ESD clamp transistor device includes a control electrode, a first current electrode coupled to the first voltage reference bus, and second current electrode coupled to the second voltage reference bus. The second ESD clamp transistor device has a second channel width different than the first channel width.
摘要翻译： 集成电路包括设置在基板上的第一I / O单元，第一I / O单元包括第一静电放电（ESD）钳位晶体管器件。 第一ESD钳位晶体管器件包括控制电极，耦合到第一电压参考总线的第一电流电极和耦合到第二电压参考总线的第二电流电极。 第一ESD钳位晶体管器件具有第一通道宽度。 集成电路还包括具有第二ESD钳位晶体管器件的第二I / O单元。 第二ESD钳位晶体管器件包括控制电极，耦合到第一电压参考总线的第一电流电极和耦合到第二电压参考总线的第二电流电极。 第二ESD钳位晶体管器件具有与第一通道宽度不同的第二通道宽度。
-
公开(公告)号：US08129226B2
公开(公告)日：2012-03-06
申请号：US12599625
申请日：2007-05-10
IPC分类号： H01L21/44
CPC分类号： H01L23/49816 , H01L23/3128 , H01L23/4951 , H01L23/49833 , H01L23/50 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/85 , H01L24/91 , H01L2224/24226 , H01L2224/32145 , H01L2224/48091 , H01L2224/48145 , H01L2224/48227 , H01L2224/48235 , H01L2224/48471 , H01L2224/49175 , H01L2224/49433 , H01L2224/4945 , H01L2224/85191 , H01L2224/85201 , H01L2224/85203 , H01L2224/85205 , H01L2924/00014 , H01L2924/01014 , H01L2924/01015 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/07802 , H01L2924/09701 , H01L2924/14 , H01L2924/15184 , H01L2924/15192 , H01L2924/15311 , H01L2924/181 , H01L2224/78 , H01L2924/00 , H01L2224/45099 , H01L2224/05599 , H01L2924/00012 , H01L2224/4554
摘要： A packaging assembly (30), such as a ball grid array package, is formed which distributes power across an interior region of an integrated circuit die (52) by using an encapsulated patterned leadframe conductor (59) that is disposed over the die (52) and bonded to a plurality of bonding pads (45) formed in a BGA carrier substrate (42) and in the interior die region, thereby electrically coupling the interior die region to an externally provided reference voltage.
摘要翻译： 形成诸如球栅阵列封装的封装组件（30），其通过使用设置在模具（52）上的封装的图案化引线框导体（59）来分布跨集成电路管芯（52）的内部区域的电力 ）并且接合到形成在BGA载体衬底（42）中的多个接合焊盘（45）和内部管芯区域中，从而将内部管芯区域电连接到外部提供的参考电压。
-
公开(公告)号：US20110020133A1
公开(公告)日：2011-01-27
申请号：US12897048
申请日：2010-10-04
申请人： James W. Miller
发明人： James W. Miller
IPC分类号： F03D1/00
CPC分类号： F03D1/0658 , F03D1/0608 , F05B2240/30 , Y02E10/721 , Y02E10/726
摘要： A pair of airfoil blades having a longitudinal axis coincident with one another. Each blade is bent at the center on the plane of the chord. Each blade has an airfoil tip blade placed at the outer most trailing edge. The blades are affixed by their root ends to opposite ends of a torsion shaft. The blade chords are offset from one another, which defines a blade pitch angle. The torsion shaft is journaled perpendicular through a driveshaft, whereas the rotation of the blades can transfer through the torsion shaft to the driveshaft and cause the driveshaft to turn, eliminating the need for a hub. The blades are adapted to pivot along with the torsion shaft. The blades lie in substantially the same plane, and are adapted for rotation in a plane orthogonal to the longitudinal axis of the driveshaft. Each blade has an airfoil shaped fluid gate valve disposed on the leading edge.
摘要翻译： 一对具有彼此重合的纵轴的翼型叶片。 每个叶片在和弦平面上的中心弯曲。 每个叶片具有放置在最外侧最后缘的翼型末端叶片。 叶片的根端固定在扭转轴的相对端。 叶片和弦彼此偏移，这限定了叶片桨距角。 扭转轴通过驱动轴垂直地轴向旋转，而叶片的旋转可以通过扭转轴传递到驱动轴，并使驱动轴转动，从而无需轮毂。 叶片适于与扭转轴一起枢转。 叶片位于基本上相同的平面中，并且适于在与驱动轴的纵向轴线正交的平面中旋转。 每个叶片具有设置在前缘上的翼型流体闸阀。
-
公开(公告)号：US07817387B2
公开(公告)日：2010-10-19
申请号：US11971591
申请日：2008-01-09
CPC分类号： H01L27/0285 , H01L2924/0002 , H01L2924/00
摘要： An electrostatic discharge (ESD) protected circuit is coupled to a power supply voltage rail and includes a multiple independent gate field effect transistor (MIGFET), a pre-driver, and a hot gate bias circuit. The MIGFET has a source/drain path coupled between an output pad and the power supply voltage rail and has a first gate terminal and a second gate terminal. The pre-driver circuit has an output. The hot gate bias circuit is coupled to the first gate terminal of the MIGFET, and the output of the pre-driver circuit is coupled to the second gate terminal of the MIGFET. The hot gate bias circuit is configured to apply a bias voltage to the first gate terminal of the MIGFET during an ESD event that increases the breakdown voltage of the MIGFET so as to better withstand the ESD event.
摘要翻译： 静电放电（ESD）保护电路耦合到电源电压轨，并包括多个独立的栅极场效应晶体管（MIGFET），预驱动器和热门偏置电路。 MIGFET具有耦合在输出焊盘和电源电压轨之间的源/漏路径，并且具有第一栅极端子和第二栅极端子。 预驱动电路有一个输出。 热门偏置电路耦合到MIGFET的第一栅极端子，并且预驱动器电路的输出耦合到MIGFET的第二栅极端子。 热门偏置电路被配置为在ESD事件期间向MIGFET的第一栅极端施加偏置电压，这增加了MIGFET的击穿电压，以便更好地承受ESD事件。
-
公开(公告)号：US07808117B2
公开(公告)日：2010-10-05
申请号：US11383653
申请日：2006-05-16
申请人： Nhat D. Vo , Tu-Anh N. Tran , Burton J. Carpenter , Dae Y. Hong , James W. Miller , Kendall D. Phillips
发明人： Nhat D. Vo , Tu-Anh N. Tran , Burton J. Carpenter , Dae Y. Hong , James W. Miller , Kendall D. Phillips
IPC分类号： H01L23/48
CPC分类号： H01L24/06 , H01L2224/02166 , H01L2224/05093 , H01L2224/05552 , H01L2224/05553 , H01L2224/05554 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/4943 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01073 , H01L2924/01079 , H01L2924/13091 , H01L2924/14 , H01L2924/00014
摘要： A pad (20) is electrically connected to a first I/O cell (14) while also physically overlying active circuitry of a second I/O cell (16). Note that although the pad (20) overlies the second I/O cell (16), the pad (20) is not electrically connected to the I/O cell (16). Such a pattern may be replicated in any desired manner so that the I/O cells (e.g. 300-310) may have a finer pitch than the corresponding pads (320-324 and 330-335). In addition, the size of the pads may be increased (e.g. pad 131 may be bigger than pad 130) while the width “c” of the I/O cells (132-135) does not have to be increased. Such a pattern (e.g. 500) may be arranged so that the area required in one or more dimensions may be minimized.
摘要翻译： 垫（20）电连接到第一I / O单元（14），同时物理地覆盖第二I / O单元（16）的有源电路。 注意，虽然焊盘（20）覆盖第二I / O单元（16），但是焊盘（20）不与I / O单元（16）电连接。 这样的图案可以以任何期望的方式复制，使得I / O单元（例如300-310）可以具有比相应的垫（320-324和330-335）更细的间距。 此外，可以增加焊盘的尺寸（例如焊盘131可能大于焊盘130），而不必增加I / O单元（132-135）的宽度“c”。 这种图案（例如500）可以被布置成使得在一个或多个维度中所需的区域可以被最小化。
-
公开(公告)号：US07777998B2
公开(公告)日：2010-08-17
申请号：US11852396
申请日：2007-09-10
IPC分类号： H02H9/00
CPC分类号： H01L27/0251 , H01L27/0292
摘要： Circuitry on integrated circuits usually includes protection against electrostatic discharge (ESD) events. A second ESD current path may be provided in addition to a first ESD current path for shunting ESD current away from circuitry to be protected during an ESD event. In addition to the standard power and ground buses used to provide power and ground voltages to the protected circuitry, one or more extra power and/or ground buses and associated circuitry may be added for improved ESD protection.
摘要翻译： 集成电路的电路通常包括防静电放电（ESD）事件。 除了第一ESD电流路径之外，还可以提供第二ESD电流路径，用于在ESD事件期间使ESD电流远离待保护的电路。 除了用于向受保护电路提供电源和接地电压的标准电源和接地总线之外，可以添加一个或多个额外的电源和/或接地总线以及相关联的电路以改善ESD保护。
-
-
-
-
-
-
-
-
-
搜索结果
70 条记录 (耗时 0.028 秒)
