公开(公告)号：US10148258B2

公开(公告)日：2018-12-04

申请号：US15279002

申请日：2016-09-28

Applicant: Mellanox Technologies, Ltd.

Inventor： Andrew Carlson ,  Carl Ramey

IPC: G06F1/04 ,  H03K3/00 ,  H03K5/06 ,  H03K5/19 ,  G06F1/32 ,  G01R31/317 ,  H03K5/135

Abstract: An integrated circuit and method are described for compensating for voltage droop on an integrated circuit using a power supply voltage monitoring circuit and a high-resolution adaptive clock stretching circuit. In some example embodiments, the method includes monitoring power supply voltage on an integrated circuit, detecting a voltage droop such as a dynamic loss of power supply in the integrated circuit, and stretching a current clock cycle, according to the detected voltage droop, to provide more time for logic on the integrated circuit to complete before a next clock cycle.

公开(公告)号：US20180091125A1

公开(公告)日：2018-03-29

申请号：US15279002

申请日：2016-09-28

Applicant: Mellanox Technologies, Ltd.

Inventor： Andrew Carlson ,  Carl Ramey

IPC: H03K5/06 ,  H03K5/19 ,  G06F1/32

CPC classification number: H03K5/06 ,  G01R31/31725 ,  G06F1/3206 ,  G06F1/324 ,  H03K5/135 ,  H03K5/19

Abstract: An integrated circuit and method are described for compensating for voltage droop on an integrated circuit using a power supply voltage monitoring circuit and a high-resolution adaptive clock stretching circuit. In some example embodiments, the method includes monitoring power supply voltage on an integrated circuit, detecting a voltage droop such as a dynamic loss of power supply in the integrated circuit, and stretching a current clock cycle, according to the detected voltage droop, to provide more time for logic on the integrated circuit to complete before a next clock cycle.

公开(公告)号：US10545905B1

公开(公告)日：2020-01-28

申请号：US15701739

申请日：2017-09-12

Applicant: Mellanox Technologies Ltd.

Inventor： Andrew Carlson ,  Shane Bell

IPC: G06F13/42 ,  G06F13/40

Abstract: A computing system comprises one or more core processors coupled to a communication network among the cores via a switch in each core and switching circuitry to forward data among cores and switches. Features include a programmable classification processor for directing packets, techniques for managing virtual functions on an IO accelerator card, packet scheduling techniques, multi-processor communication using shared FIFOs, programmable duty cycle adjustment and delay adjustment circuits, a new class of instructions that use a ready bit, and cache coherence and memory ordering techniques.