Data processing unit with transparent root complex

    公开(公告)号:US20240143526A1

    公开(公告)日:2024-05-02

    申请号:US17976909

    申请日:2022-10-31

    IPC分类号: G06F13/28 G06F13/42

    CPC分类号: G06F13/28 G06F13/4221

    摘要: Computing apparatus includes a central processing unit (CPU) and a root complex connected to the CPU and to a first peripheral component bus, which has at least a first downstream port for connection to at least one peripheral device. Switching logic has an upstream port for connection to a second downstream port on a second peripheral component bus of a host computer, and is connected to the root complex so that when a peripheral device is connected to the first downstream port on the first peripheral component bus, the switching logic presents the peripheral device to the host computer in an address space of the second peripheral component bus.

    LINK AGGREGATION IN INFINIBAND NETWORKS
    2.
    发明公开

    公开(公告)号:US20240259298A1

    公开(公告)日:2024-08-01

    申请号:US18162174

    申请日:2023-01-31

    IPC分类号: H04L45/24 H04L61/103

    摘要: Systems and methods herein are for one or more processing units of a subnet manger (SM) to communicate configuration information with at least one subnet management agent (SMA) that is associated with at least one switch and with a host machine, the configuration information to enable the at least one switch to configure a forwarding table based in part on a mapping of at least one virtual network address to physical network addresses of two or more physical ports of the host machine, and the configuration information to enable the host machine to communicate with other host machines using the at least one switch and the at least one virtual network address.

    Data processing unit with transparent root complex

    公开(公告)号:US12117948B2

    公开(公告)日:2024-10-15

    申请号:US17976909

    申请日:2022-10-31

    IPC分类号: G06F13/28 G06F13/42

    CPC分类号: G06F13/28 G06F13/4221

    摘要: Computing apparatus includes a central processing unit (CPU) and a root complex connected to the CPU and to a first peripheral component bus, which has at least a first downstream port for connection to at least one peripheral device. Switching logic has an upstream port for connection to a second downstream port on a second peripheral component bus of a host computer, and is connected to the root complex so that when a peripheral device is connected to the first downstream port on the first peripheral component bus, the switching logic presents the peripheral device to the host computer in an address space of the second peripheral component bus.