公开(公告)号：US10015112B2

公开(公告)日：2018-07-03

申请号：US14961923

申请日：2015-12-08

Applicant: Mellanox Technologies TLV Ltd.

Inventor： Amir Roitshtein ,  Niv Aibester ,  Barak Gafni ,  George Elias

IPC: H04L12/931 ,  H04L12/861 ,  H04L12/741

CPC classification number: H04L49/201 ,  H04L45/745 ,  H04L49/205 ,  H04L49/9005

Abstract: Communication apparatus includes multiple interfaces connected to a packet data network. A memory is coupled to the interfaces and configured as a buffer to contain packets received through ingress interfaces while awaiting transmission to the network via respective egress interfaces. Packet processing logic is configured, upon receipt of a multicast packet through an ingress interface, to identify a number of the egress interfaces through which respective copies of the multicast packet are to be transmitted, to allocate a space in the buffer for storage of a single copy of the multicast packet, to replicate and transmit multiple copies of the stored copy of the multicast packet through the egress interfaces, to maintain a count of the replicated copies that have been transmitted, and when the count reaches the identified number, to release the allocated space in the buffer.

公开(公告)号：US11500737B2

公开(公告)日：2022-11-15

申请号：US16417669

申请日：2019-05-21

Applicant: MELLANOX TECHNOLOGIES TLV LTD.

Inventor： Niv Aibester ,  Shmuel Shichrur ,  Barak Gafni

IPC: G06F11/14 ,  G06F9/54 ,  H04L43/022

Abstract: A network element includes multiple ports configured to communicate over a network, a buffer memory, a snapshot memory, and circuitry. The circuitry is configured to forward packets between the ports, to temporarily store information associated with the packets in the buffer memory, to continuously write at least part of the information to the snapshot memory concurrently with storage of the information in the buffer memory, and, in response to at least one predefined diagnostic event, to stop writing of the information to the snapshot memory, so as to create in the snapshot memory a coherent snapshot corresponding to a time of the diagnostic event.

公开(公告)号：US20210226895A1

公开(公告)日：2021-07-22

申请号：US16746879

申请日：2020-01-19

Applicant: MELLANOX TECHNOLOGIES TLV LTD.

Inventor： Niv Aibester ,  Aviv Kfir ,  Gil Levy ,  Liron Mula

IPC: H04L12/813 ,  H04L12/851 ,  H04L12/911 ,  H04L12/823

Abstract: Apparatus for global policing of a bandwidth of a flow, the apparatus including a network device including a local policer configured to perform bandwidth policing on the flow within the network device, and a communications module configured to: send local policer state information from the local policer to a remote global policer, and receive policer state information from the remote global policer and update the local policer state information based on the remote global policer state information, Related apparatus and methods are also provided.

公开(公告)号：US10938720B2

公开(公告)日：2021-03-02

申请号：US16420217

申请日：2019-05-23

Applicant: MELLANOX TECHNOLOGIES TLV LTD.

Inventor： Niv Aibester ,  Gil Levy ,  Nir Monovich

IPC: H04L12/747 ,  H04L12/741

Abstract: A network element includes multiple ports, a memory, multiple processors and cache-flushing circuitry. The multiple ports are configured to serve as ingress and egress ports for receiving and transmitting packets from and to a network. The memory is configured to store a forwarding table including rules that specify forwarding of the packets from the ingress ports to the egress ports. The multiple processors are configured to process the packets in accordance with the rules. The two or more cache memories are each configured to cache a respective copy of one or more of the rules, for use by the multiple processors. The cache-flushing circuitry is configured to trigger flushing operations of copies of rules in the cache memories in response to changes in the forwarding table, and to reduce a likelihood of simultaneous accesses to the forwarding table for updating multiple cache memories, by de-correlating or diluting the flushing operations.

公开(公告)号：US20200374230A1

公开(公告)日：2020-11-26

申请号：US16420217

申请日：2019-05-23

Applicant: MELLANOX TECHNOLOGIES TLV LTD.

Inventor： Niv Aibester ,  Gil Levy ,  Nir Monovich

IPC: H04L12/747 ,  H04L12/741

Abstract: A network element includes multiple ports, a memory, multiple processors and cache-flushing circuitry. The multiple ports are configured to serve as ingress and egress ports for receiving and transmitting packets from and to a network. The memory is configured to store a forwarding table including rules that specify forwarding of the packets from the ingress ports to the egress ports. The multiple processors are configured to process the packets in accordance with the rules. The two or more cache memories are each configured to cache a respective copy of one or more of the rules, for use by the multiple processors. The cache-flushing circuitry is configured to trigger flushing operations of copies of rules in the cache memories in response to changes in the forwarding table, and to reduce a likelihood of simultaneous accesses to the forwarding table for updating multiple cache memories, by de-correlating or diluting the flushing operations.

公开(公告)号：US20220224585A1

公开(公告)日：2022-07-14

申请号：US17145341

申请日：2021-01-10

Applicant: MELLANOX TECHNOLOGIES TLV LTD.

Inventor： Niv Aibester ,  Aviv Kfir ,  Gil Levy ,  Liron Mula

IPC: H04L12/24

Abstract: A network-connected device includes at least one communication port, packet processing circuitry and Diagnostics Direct Memory Access (DMA) Circuitry (DDC). The at least one communication port is configured to communicate packets over a network. The packet processing circuitry is configured to receive, buffer, process and transmit the packets. The DDC is configured to receive a definition of (i) one or more diagnostic events, and (ii) for each diagnostic event, a corresponding list of diagnostic data that is generated in the packet processing circuitry and that pertains to the diagnostic event, and, responsively to occurrence of a diagnostic event, to gather the corresponding list of diagnostic data from the packet processing circuitry.

公开(公告)号：US11171884B2

公开(公告)日：2021-11-09

申请号：US16351684

申请日：2019-03-13

Applicant: MELLANOX TECHNOLOGIES TLV LTD.

Inventor： Liron Mula ,  Niv Aibester ,  Barak Gafni

IPC: H04L12/935 ,  H04L12/867 ,  H04L12/813 ,  H04L12/931 ,  H04L12/801 ,  H04L12/865

Abstract: In one embodiment, a network device includes multiple ports to be connected to a packet data network so as to serve as both ingress and egress ports in receiving and forwarding of data packets including unicast and multicast data packets, a memory coupled to the ports and to contain a combined unicast-multicast user-pool storing the received unicast and multicast data packets, and packet processing logic to compute a combined unicast-multicast user-pool free-space based on counting only once at least some of the multicast packets stored once in the combined unicast-multicast user-pool, compute an occupancy of an egress queue by counting a space used by the data packets of the egress queue in the combined unicast-multicast user-pool, apply an admission policy to a received data packet for entry into the egress queue based on at least the computed occupancy of the egress queue and the computed combined unicast-multicast user-pool free-space.

公开(公告)号：US09985910B2

公开(公告)日：2018-05-29

申请号：US15194585

申请日：2016-06-28

Applicant: Mellanox Technologies TLV Ltd.

Inventor： Barak Gafni ,  Benny Koren ,  George Elias ,  Itamar Rabenstein ,  Eyal Srebro ,  Sagi Kuks ,  Niv Aibester

IPC: H04L12/947 ,  H04L12/863 ,  H04L12/851 ,  H04L12/801

CPC classification number: H04L49/25 ,  H04L47/12 ,  H04L47/24 ,  H04L47/245 ,  H04L47/6295 ,  H04L49/253

Abstract: A method for communication includes receiving and forwarding packets in multiple flows to respective egress interfaces of a switching element for transmission to a network. For each of one or more of the egress interfaces, in each of a succession of arbitration cycles, a respective number of the packets in each of the plurality of the flows that are queued for transmission through the egress interface is assessed, and the flows for which the respective number is zero are assigned to a first group, while the flows for which the respective number is non-zero are assigned to a second group. The received packets that have been forwarded to the egress interface and belong to the flows in the first group are transmitted with a higher priority than the flows in the second group.

公开(公告)号：US11637739B2

公开(公告)日：2023-04-25

申请号：US17145341

申请日：2021-01-10

Applicant: MELLANOX TECHNOLOGIES TLV LTD.

Inventor： Niv Aibester ,  Aviv Kfir ,  Gil Levy ,  Liron Mula

IPC: H04L41/06

Abstract: A network-connected device includes at least one communication port, packet processing circuitry and Diagnostics Direct Memory Access (DMA) Circuitry (DDC). The at least one communication port is configured to communicate packets over a network. The packet processing circuitry is configured to receive, buffer, process and transmit the packets. The DDC is configured to receive a definition of (i) one or more diagnostic events, and (ii) for each diagnostic event, a corresponding list of diagnostic data that is generated in the packet processing circuitry and that pertains to the diagnostic event, and, responsively to occurrence of a diagnostic event, to gather the corresponding list of diagnostic data from the packet processing circuitry.

公开(公告)号：US11558316B2

公开(公告)日：2023-01-17

申请号：US17175716

申请日：2021-02-15

Applicant: MELLANOX TECHNOLOGIES TLV LTD.

Inventor： Liron Mula ,  Idan Matari ,  Niv Aibester ,  George Elias ,  Lion Levi

IPC: H04L12/861 ,  H04L49/90 ,  H04L47/32 ,  H04L49/9047

Abstract: A network device includes multiple ports, multiple buffer slices, a controller, and buffer control circuitry. The multiple ports are configured to communicate packets over a network. The multiple buffer slices are linked respectively to the multiple ports. The controller is configured to allocate a group of two or more of the buffer slices to a selected port among the ports. The buffer control circuitry is configured to buffer the packets, communicated via the selected port, in the group of the buffer slices, using zero-copy buffering.