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公开(公告)号：US20170289066A1
公开(公告)日：2017-10-05
申请号：US15086990
申请日：2016-03-31
Applicant: Mellanox Technologies TLV Ltd.
Inventor： Zachy Haramaty , Ran Ravid , Oded Wertheim
IPC: H04L12/939 , H04L12/835 , H04L12/807 , H04L12/825
CPC classification number: H04L49/552 , H04L47/263 , H04L47/27 , H04L47/30
Abstract: Apparatuses and methods are described that provide for credit based flow control in a network in which a public buffer is supported at a receiver node, where a transmitter node can control the use of the public buffer. In particular, the transmitter node determines a buffer credit value (TCRi) for each virtual lane of the transmitter node. The buffer credit value (TCRi) is negative (e.g., less than 0) in an instance in which a respective virtual lane private buffer is fully used and thus reflects a loan of credits from the public buffer. In addition, the transmitter node knows the needed buffer size per virtual lane for transmitting a packet in advance based on the round trip time (RTT) and maximum transmission unit (MTU) for the packet and is precluded from consuming more space on the public buffer than required to meet RTT.
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公开(公告)号：US10057017B2
公开(公告)日：2018-08-21
申请号：US15470928
申请日：2017-03-28
Applicant: Mellanox Technologies TLV Ltd.
Inventor： Liron Mula , Ran Ravid , Oded Wertheim , Ran Sela , Roy Kriss
CPC classification number: H04L1/16 , H04L1/0041 , H04L1/0045 , H04L1/0052 , H04L69/324
Abstract: Communication apparatus includes an input circuit, which receives a sequence of symbols arranged in a series of data blocks, including data symbols that encode the data and forward error correction (FEC) symbols that encode an error correction code. The input circuit decodes the data encoded by the data symbols and passes the decoded data to a buffer for output to a data link layer interface irrespective of the FEC symbols. An error correction circuit receives the data and the error correction code from the input circuit, and upon detecting an error in a given data block in the series, passes the corrected data from the given data block to the buffer for output to the data link layer interface in place of the data from the given data block that the input circuit decoded and passed to the buffer.
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公开(公告)号：US10419329B2
公开(公告)日：2019-09-17
申请号：US15473643
申请日：2017-03-30
Applicant: Mellanox Technologies TLV Ltd.
Inventor： Lion Levi , George Elias , Oded Wertheim , Amiad Marelli , Miriam Menes , Itamar Rabenstein , Noam Avital , Evyatar Romlet , Ofir Merdler
IPC: H04L12/761 , H04L1/16
Abstract: Communication apparatus includes a plurality of interfaces for receiving and transmitting data packets from and to a network and a memory, which receives and stores context data with respect to multicast groups. Packet processing circuitry establishes reliable connections over the network with the receiving nodes in the multicast groups, and upon receiving from a packet source on the network an incoming unicast packet containing multicast data and containing multicast metadata that identifies a multicast group, sends an acknowledgment of the incoming unicast packet to the packet source, reads the context data from the memory with respect to the identified multicast group, and transmits multiple outgoing unicast packets containing the multicast data via respective egress interfaces to the receiving nodes in the multicast group over the reliable connections.
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Patent Agency Ranking
公开(公告)号：US20180287928A1
公开(公告)日：2018-10-04
申请号：US15473643
申请日：2017-03-30
Applicant: Mellanox Technologies TLV Ltd.
Inventor： Lion Levi , George Elias , Oded Wertheim , Amiad Marelli , Miriam Menes , Itamar Rabenstein , Noam Avital , Evyatar Romlet , Ofir Merdler
IPC: H04L12/761
CPC classification number: H04L45/16 , H04L1/16 , H04L1/1835 , H04L1/188 , H04L2001/0093
Abstract: Communication apparatus includes a plurality of interfaces for receiving and transmitting data packets from and to a network and a memory, which receives and stores context data with respect to multicast groups. Packet processing circuitry establishes reliable connections over the network with the receiving nodes in the multicast groups, and upon receiving from a packet source on the network an incoming unicast packet containing multicast data and containing multicast metadata that identifies a multicast group, sends an acknowledgment of the incoming unicast packet to the packet source, reads the context data from the memory with respect to the identified multicast group, and transmits multiple outgoing unicast packets containing the multicast data via respective egress interfaces to the receiving nodes in the multicast group over the reliable connections.
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公开(公告)号：US10079782B2
公开(公告)日：2018-09-18
申请号：US15086990
申请日：2016-03-31
Applicant: Mellanox Technologies TLV Ltd.
Inventor： Zachy Haramaty , Ran Ravid , Oded Wertheim
IPC: H04L12/939 , H04L12/835 , H04L12/807 , H04L12/825
CPC classification number: H04L49/552 , H04L47/263 , H04L47/27 , H04L47/30
Abstract: Apparatuses and methods are described that provide for credit based flow control in a network in which a public buffer is supported at a receiver node, where a transmitter node can control the use of the public buffer. In particular, the transmitter node determines a buffer credit value (TCRi) for each virtual lane of the transmitter node. The buffer credit value (TCRi) is negative (e.g., less than 0) in an instance in which a respective virtual lane private buffer is fully used and thus reflects a loan of credits from the public buffer. In addition, the transmitter node knows the needed buffer size per virtual lane for transmitting a packet in advance based on the round trip time (RTT) and maximum transmission unit (MTU) for the packet and is precluded from consuming more space on the public buffer than required to meet RTT.
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公开(公告)号：US20170201350A1
公开(公告)日：2017-07-13
申请号：US15470928
申请日：2017-03-28
Applicant: Mellanox Technologies TLV Ltd.
Inventor： Liron Mula , Ran Ravid , Oded Wertheim , Ran Sela , Roy Kriss
CPC classification number: H04L1/16 , H04L1/0041 , H04L1/0045 , H04L1/0052 , H04L69/324
Abstract: Communication apparatus includes an input circuit, which receives a sequence of symbols arranged in a series of data blocks, including data symbols that encode the data and forward error correction (FEC) symbols that encode an error correction code. The input circuit decodes the data encoded by the data symbols and passes the decoded data to a buffer for output to a data link layer interface irrespective of the FEC symbols. An error correction circuit receives the data and the error correction code from the input circuit, and upon detecting an error in a given data block in the series, passes the corrected data from the given data block to the buffer for output to the data link layer interface in place of the data from the given data block that the input circuit decoded and passed to the buffer.
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公开(公告)号：US09673934B2
公开(公告)日：2017-06-06
申请号：US14870031
申请日：2015-09-30
Applicant: Mellanox Technologies TLV Ltd.
Inventor： Liron Mula , Ran Ravid , Oded Wertheim , Ran Sela , Roy Kriss
CPC classification number: H04L1/0045 , H04L1/0041 , H04L1/0053 , H04L69/324
Abstract: Communication apparatus includes a PHY interface, which is configured to receive over a communication link and to decode a sequence of symbols arranged in a series of data blocks. The PHY interface includes an error correction circuit, which when actuated, corrects errors in decoded data symbols using FEC symbols in the data blocks. The decoded data include data packets containing respective error detection codes. A memory buffers the data blocks received by the PHY interface. A data link layer interface receives the data packets from the PHY interface, checks the data packets using respective error detection codes, and upon detecting an error in a given data packet, signals the PHY interface to read from the memory at least one buffered data block that contains the given data packet while actuating the error correction circuit to correct the error using the FEC symbols in the at least one buffered data block.
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公开(公告)号：US20170093526A1
公开(公告)日：2017-03-30
申请号：US14870031
申请日：2015-09-30
Applicant: Mellanox Technologies TLV Ltd.
Inventor： Liron Mula , Ran Ravid , Oded Wertheim , Ran Sela , Roy Kriss
CPC classification number: H04L1/0045 , H04L1/0041 , H04L1/0053 , H04L69/324
Abstract: Communication apparatus includes a PHY interface, which is configured to receive over a communication link and to decode a sequence of symbols arranged in a series of data blocks. The PHY interface includes an error correction circuit, which when actuated, corrects errors in decoded data symbols using FEC symbols in the data blocks. The decoded data include data packets containing respective error detection codes. A memory buffers the data blocks received by the PHY interface. A data link layer interface receives the data packets from the PHY interface, checks the data packets using respective error detection codes, and upon detecting an error in a given data packet, signals the PHY interface to read from the memory at least one buffered data block that contains the given data packet while actuating the error correction circuit to correct the error using the FEC symbols in the at least one buffered data block.
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