公开(公告)号：US10218642B2

公开(公告)日：2019-02-26

申请号：US15469643

申请日：2017-03-27

Applicant: Mellanox Technologies TLV Ltd.

Inventor： Liron Mula ,  Sagi Kuks ,  George Elias ,  Eyal Srebro ,  Ofir Merdler ,  Amiad Marelli ,  Lion Levi ,  Oded Zemer ,  Yoav Benros

IPC: H04L12/935 ,  H04L12/933 ,  H04L12/937 ,  H04L12/931 ,  H04L12/861

Abstract: A network switch includes circuitry and multiple ports, including multiple input ports and at least one output port, configured to connect to a communication network. The circuitry includes multiple distinct-flow counters, which are each associated with a respective input port and with the output port, and which are configured to estimate respective distinct-flow counts of distinct data flows received via the respective input ports and destined to the output port. The circuitry is configured to store packets that are destined to the output port and were received via the multiple input ports in multiple queues, to determine a transmission schedule for the packets stored in the queues, based on the estimated distinct-flow counts, and to transmit the packets via the output port in accordance with the determined transmission schedule.

公开(公告)号：US20210234753A1

公开(公告)日：2021-07-29

申请号：US16750019

申请日：2020-01-23

Applicant: MELLANOX TECHNOLOGIES TLV LTD.

Inventor： Ortal Ben-Moshe ,  Lion Levi ,  Itamar Rabenstein ,  Idan Matari ,  Noam Michaelis ,  Ofir Merdler ,  Evyatar Romlet

IPC: H04L12/24 ,  H04L12/911 ,  H04L1/00 ,  H04L29/08

Abstract: A network element includes a plurality of ports, multiple computational modules, configurable forwarding circuitry and a central block. The ports include child ports coupled to child network elements or network nodes and parent ports coupled to parent network elements. The computational modules collectively perform a data reduction operation of a data reduction protocol. The forwarding circuitry interconnects among ports and computational modules. The central block receives a request indicative of child ports, a parent port, and computational modules required for performing reduction operations on data received via the child ports, for producing reduced data destined to the parent port, to derive from the request a topology that interconnects among the child ports, parent port and computational modules for performing the data reduction operations and to forward the reduced data for transmission to the selected parent port, and to configure the forwarding circuitry to apply the topology.

公开(公告)号：US10938715B2

公开(公告)日：2021-03-02

申请号：US16436945

申请日：2019-06-11

Applicant: MELLANOX TECHNOLOGIES TLV LTD.

Inventor： Ofir Merdler ,  George Elias ,  Yuval Shpigelman ,  Eyal Srebro ,  Sagi Kuks

IPC: H04L12/773 ,  H04L12/935 ,  H04L12/933 ,  H04L12/861

Abstract: A network element includes output ports, a crossbar fabric and a scheduler. The output ports are organized in groups of multiple output ports selectable over predefined time slots in accordance with a cyclic mapping assigned to each group. In each time slot, the crossbar fabric routes to fabric outputs data received from the buffers via fabric inputs, in accordance with a routing plan. The scheduler determines and applies the routing plan for transmitting packets from the buffers to the communication network via the crossbar fabric and output ports. When in a given time slot, a required readout rate from a given buffer exceeds a maximum rate, the scheduler selects a group of the output ports to which the given buffer is routed in that time slot, and modifies the cyclic mapping for that group to reduce the required readout rate from the given buffer in the given time slot.

公开(公告)号：US10419329B2

公开(公告)日：2019-09-17

申请号：US15473643

申请日：2017-03-30

Applicant: Mellanox Technologies TLV Ltd.

Inventor： Lion Levi ,  George Elias ,  Oded Wertheim ,  Amiad Marelli ,  Miriam Menes ,  Itamar Rabenstein ,  Noam Avital ,  Evyatar Romlet ,  Ofir Merdler

IPC: H04L12/761 ,  H04L1/16

Abstract: Communication apparatus includes a plurality of interfaces for receiving and transmitting data packets from and to a network and a memory, which receives and stores context data with respect to multicast groups. Packet processing circuitry establishes reliable connections over the network with the receiving nodes in the multicast groups, and upon receiving from a packet source on the network an incoming unicast packet containing multicast data and containing multicast metadata that identifies a multicast group, sends an acknowledgment of the incoming unicast packet to the packet source, reads the context data from the memory with respect to the identified multicast group, and transmits multiple outgoing unicast packets containing the multicast data via respective egress interfaces to the receiving nodes in the multicast group over the reliable connections.

公开(公告)号：US20180287928A1

公开(公告)日：2018-10-04

申请号：US15473643

申请日：2017-03-30

Applicant: Mellanox Technologies TLV Ltd.

Inventor： Lion Levi ,  George Elias ,  Oded Wertheim ,  Amiad Marelli ,  Miriam Menes ,  Itamar Rabenstein ,  Noam Avital ,  Evyatar Romlet ,  Ofir Merdler

IPC: H04L12/761

CPC classification number: H04L45/16 ,  H04L1/16 ,  H04L1/1835 ,  H04L1/188 ,  H04L2001/0093

Abstract: Communication apparatus includes a plurality of interfaces for receiving and transmitting data packets from and to a network and a memory, which receives and stores context data with respect to multicast groups. Packet processing circuitry establishes reliable connections over the network with the receiving nodes in the multicast groups, and upon receiving from a packet source on the network an incoming unicast packet containing multicast data and containing multicast metadata that identifies a multicast group, sends an acknowledgment of the incoming unicast packet to the packet source, reads the context data from the memory with respect to the identified multicast group, and transmits multiple outgoing unicast packets containing the multicast data via respective egress interfaces to the receiving nodes in the multicast group over the reliable connections.

公开(公告)号：US11252027B2

公开(公告)日：2022-02-15

申请号：US16750019

申请日：2020-01-23

Applicant: MELLANOX TECHNOLOGIES TLV LTD.

Inventor： Ortal Ben-Moshe ,  Lion Levi ,  Itamar Rabenstein ,  Idan Matari ,  Noam Michaelis ,  Ofir Merdler ,  Evyatar Romlet

IPC: H04L12/24 ,  H04L12/911 ,  H04L1/00 ,  H04L29/08

Abstract: A network element includes a plurality of ports, multiple computational modules, configurable forwarding circuitry and a central block. The ports include child ports coupled to child network elements or network nodes and parent ports coupled to parent network elements. The computational modules collectively perform a data reduction operation of a data reduction protocol. The forwarding circuitry interconnects among ports and computational modules. The central block receives a request indicative of child ports, a parent port, and computational modules required for performing reduction operations on data received via the child ports, for producing reduced data destined to the parent port, to derive from the request a topology that interconnects among the child ports, parent port and computational modules for performing the data reduction operations and to forward the reduced data for transmission to the selected parent port, and to configure the forwarding circuitry to apply the topology.

公开(公告)号：US20180278549A1

公开(公告)日：2018-09-27

申请号：US15469643

申请日：2017-03-27

Applicant: Mellanox Technologies TLV Ltd.

Inventor： Liron Mula ,  Sagi Kuks ,  George Elias ,  Eyal Srebro ,  Ofir Merdler ,  Amiad Marelli ,  Lion Levi ,  Oded Zemer ,  Yoav Benros

IPC: H04L12/935 ,  H04L12/933 ,  H04L12/937 ,  H04L12/931 ,  H04L12/861

CPC classification number: H04L49/3018 ,  H04L49/1523 ,  H04L49/254 ,  H04L49/3072 ,  H04L49/65 ,  H04L49/90

Abstract: A network switch includes circuitry and multiple ports, including multiple input ports and at least one output port, configured to connect to a communication network. The circuitry includes multiple distinct-flow counters, which are each associated with a respective input port and with the output port, and which are configured to estimate respective distinct-flow counts of distinct data flows received via the respective input ports and destined to the output port. The circuitry is configured to store packets that are destined to the output port and were received via the multiple input ports in multiple queues, to determine a transmission schedule for the packets stored in the queues, based on the estimated distinct-flow counts, and to transmit the packets via the output port in accordance with the determined transmission schedule.