公开(公告)号：US20170193155A1

公开(公告)日：2017-07-06

申请号：US15400904

申请日：2017-01-06

申请人： Mentor Graphics Corporation

发明人： Xijiang Lin ,  Wu-Tung Cheng ,  Janusz Rajski

IPC分类号： G06F17/50

CPC分类号： G01R31/318371 ,  G01R31/318307 ,  G01R31/318364 ,  G06F17/5022 ,  G06F17/5027 ,  G06F17/5045 ,  G06F17/5059

摘要： Aspects of the disclosed technology relate to techniques of test pattern generation based on the cell transition fault model. An assignment for two consecutive clock cycles at inputs of a complex cell in a circuit design is determined based on a gate-level representation of the circuit design. The assignment includes a first transition at one of the inputs which is sensitized by remaining part of the assignment to cause a second transition at an output of the complex cell. A test pattern that generates the assignment at the inputs and propagates a value at the output corresponding to the second clock cycle of the two consecutive clock cycles from the output to an observation point is then derived based on the gate-level representation.

公开(公告)号：US20150323600A1

公开(公告)日：2015-11-12

申请号：US14803866

申请日：2015-07-20

申请人： Mentor Graphics Corporation

发明人： Xijiang Lin ,  Kun-Han Tsai ,  Mark Kassab ,  Chen Wang ,  Janusz Rajski

IPC分类号： G01R31/3177

CPC分类号： G01R31/318328 ,  G01R31/3177 ,  G01R31/31835 ,  G01R31/318357 ,  G06F17/5009

摘要： Disclosed herein are exemplary methods, apparatus, and systems for performing timing-aware automatic test pattern generation (ATPG) that can be used, for example, to improve the quality of a test set generated for detecting delay defects or holding time defects. In certain embodiments, timing information derived from various sources (e.g. from Standard Delay Format (SDF) files) is integrated into an ATPG tool. The timing information can be used to guide the test generator to detect the faults through certain paths (e.g., paths having a selected length, or range of lengths, such as the longest or shortest paths). To avoid propagating the faults through similar paths repeatedly, a weighted random method can be used to improve the path coverage during test generation. Experimental results show that significant test quality improvement can be achieved when applying embodiments of timing-aware ATPG to industrial designs.

摘要翻译： 这里公开了用于执行定时感知自动测试模式生成（ATPG）的示例性方法，装置和系统，其可以用于例如为了提高用于检测延迟缺陷或保持时间缺陷而产生的测试集的质量。 在某些实施例中，从各种源（例如，从标准延迟格式（SDF）文件）导出的定时信息被集成到ATPG工具中。 定时信息可用于引导测试发生器通过某些路径（例如，具有选定长度的路径或长度范围，例如最长或最短路径）来检测故障。 为了避免重复通过类似路径传播故障，可以使用加权随机方法来提高测试生成过程中的路径覆盖。 实验结果表明，当将工业设计应用于定时识别ATPG的实施例时，可以实现显着的测试质量改进。

公开(公告)号：US20150153410A1

公开(公告)日：2015-06-04

申请号：US14557739

申请日：2014-12-02

申请人： Mentor Graphics Corporation

发明人： Xijiang Lin ,  Mark A. Kassab ,  Janusz Rajski

IPC分类号： G01R31/3177 ,  G01R31/3185 ,  G01R31/3183

CPC分类号： G01R31/318536 ,  G01R31/318547

摘要： Various aspects of the disclosed techniques relate to using dynamic shift for test pattern compression. Scan chains are divided into segments. Non-shift clock cycles are added to one or more segments to make an uncompressible test pattern compressible. The one or more segments may be selected based on compressibility, the number of specified bits and/or the location on the scan chains. A dynamic shift controller may be employed to control the dynamic shift.

摘要翻译： 所公开的技术的各个方面涉及使用用于测试图案压缩的动态移位。 扫描链分为几段。 非移位时钟周期被添加到一个或多个段以使不可压缩的测试图案可压缩。 可以基于可压缩性，指定位的数量和/或扫描链上的位置来选择一个或多个段。 可以采用动态变速控制器来控制动态位移。

公开(公告)号：US20220065929A1

公开(公告)日：2022-03-03

申请号：US17004288

申请日：2020-08-27

申请人： Mentor Graphics Corporation

发明人： Xijiang Lin ,  Wu-Tung Cheng ,  Takeo Kobayashi ,  Andreas Glowatz

IPC分类号： G01R31/317 ,  G01R31/3177

摘要： This application discloses a computing system implementing an automatic test pattern generation tool to convert a transistor-level model of a library cell describing a digital circuit into a switch-level model of the library cell, generate test patterns configured to enable detection of target defects injected into the switch-level model of the library cell, and bifurcate the test patterns into a first subset of the test patterns and a second set of the test patterns based on detection types for the target defects enabled by the test patterns. The computing system can implement a cell model generation tool to perform an analog simulation of the transistor-level model of the library cell using the second subset of the test patterns to verify that they enable detection of target defects, while skipping performance of the analog simulation of the transistor-level model of the library cell using the first subset of the test patterns.

公开(公告)号：US20150248515A1

公开(公告)日：2015-09-03

申请号：US14633999

申请日：2015-02-27

申请人： Mentor Graphics Corporation

发明人： Xijiang Lin ,  Ting-Pu Tai ,  Wu-Tung Cheng ,  Takeo Kobayashi

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G01R31/2803 ,  G01R31/2815 ,  G01R31/2818 ,  G01R31/2851 ,  G01R31/2856 ,  G01R31/317 ,  G01R31/31704 ,  G01R31/318533 ,  G01R31/318586 ,  G06F17/5022 ,  G06F17/5068 ,  G06F17/5072 ,  G06F17/5081 ,  G06F2217/14

摘要： Various aspects of the disclosed technology relate to techniques of selecting scan cells from state elements for partial scan designs. Signal probability values for logic gates in a circuit design are first determined. Based on the signal probability values, next-state capture probability values for state elements in the circuit design are computed. Based on the next-state capture probability values, scan cells are selected from the state elements. Scan cells may be further selected based on continuously-updated control weight values and observation weight values associated with the state elements.

摘要翻译： 所公开技术的各个方面涉及从用于部分扫描设计的状态元素中选择扫描单元的技术。 首先确定电路设计中逻辑门的信号概率值。 基于信号概率值，计算电路设计中状态元素的下一状态捕获概率值。 基于下一状态捕获概率值，从状态元素中选择扫描单元。 可以基于与状态元素相关联的持续更新的控制权重值和观察权重值来进一步选择扫描单元。

公开(公告)号：US08996941B2

公开(公告)日：2015-03-31

申请号：US13914529

申请日：2013-06-10

申请人： Mentor Graphics Corporation

发明人： Xijiang Lin ,  Janusz Rajski

IPC分类号： G01R31/28 ,  G01R31/3177 ,  G01R31/3185

CPC分类号： G01R31/3177 ,  G01R31/318544 ,  G01R31/318547

摘要： Background scan cells are selected from scan cells in a circuit based on specified bit distribution information for a plurality of test cubes generated for testing the circuit. A main portion and a background portion are then determined for each test cube in the plurality of test cubes. The background portion corresponds to the background scan cells. Test cubes in the plurality of test cubes that have compatible main portions are merged into test cube groups. Each test cube group in the test cube groups comprises a main test cube and background test cubes. A main test cube, supplied by a tester or a decompressor, may be shifted into the scan chains. A background test cube may be shifted into background chains and be inserted into the main test cube in the scan chains based on control signals.

摘要翻译： 基于用于测试电路产生的多个测试立方体的指定位分布信息，从电路中的扫描单元中选择背景扫描单元。 然后，对于多个测试立方体中的每个测试立方体，确定主要部分和背景部分。 背景部分对应于背景扫描单元。 在具有兼容的主要部分的多个测试立方体中测试立方体被合并到测试立方体组中。 测试多维数据集中的每个测试立方体组都包含主测试立方体和后台测试立方体。 由测试器或解压缩器提供的主要测试立方体可以被移动到扫描链中。 背景测试立方体可以被转移到背景链中，并且基于控制信号插入到扫描链中的主测试立方体中。

公开(公告)号：US20150040087A1

公开(公告)日：2015-02-05

申请号：US14517609

申请日：2014-10-17

申请人： Mentor Graphics Corporation

发明人： Xijiang Lin ,  Yu Huang ,  Wu-Tung Cheng

IPC分类号： G01R31/317 ,  G06F17/50 ,  G01R31/3177

CPC分类号： G06F17/5022 ,  G01R31/318575

摘要： Aspects of the disclosed techniques relate to techniques for identifying power sensitive scan cells. Signal probability values for signal lines in a circuit design are first computed, wherein the signal lines comprise signal lines associated with scan cells in the circuit design. Toggling probability values are then computed based on the signal probability values, wherein the toggling probability values comprise toggling rate values for the scan cells. Toggling rate reduction values are then computed based on the toggling probability values, wherein the toggling rate reduction values comprise toggling rate reduction values for the scan cells. Finally, scan cells having high toggling rate reduction values are identified.

摘要翻译： 所公开技术的方面涉及用于识别功率敏感扫描单元的技术。 首先计算电路设计中的信号线的信号概率值，其中信号线包括与电路设计中的扫描单元相关联的信号线。 然后基于信号概率值计算切换概率值，其中切换概率值包括扫描单元的切换速率值。 然后基于切换概率值计算切换速率降低值，其中切换速率降低值包括扫描单元的切换速率降低值。 最后，识别具有高切换速率降低值的扫描单元。

公开(公告)号：US11635462B2

公开(公告)日：2023-04-25

申请号：US17004288

申请日：2020-08-27

申请人： Mentor Graphics Corporation

发明人： Xijiang Lin ,  Wu-Tung Cheng ,  Takeo Kobayashi ,  Andreas Glowatz

IPC分类号： G01R31/00 ,  G01R31/317 ,  G01R31/3177

摘要： This application discloses a computing system implementing an automatic test pattern generation tool to convert a transistor-level model of a library cell describing a digital circuit into a switch-level model of the library cell, generate test patterns configured to enable detection of target defects injected into the switch-level model of the library cell, and bifurcate the test patterns into a first subset of the test patterns and a second set of the test patterns based on detection types for the target defects enabled by the test patterns. The computing system can implement a cell model generation tool to perform an analog simulation of the transistor-level model of the library cell using the second subset of the test patterns to verify that they enable detection of target defects, while skipping performance of the analog simulation of the transistor-level model of the library cell using the first subset of the test patterns.

公开(公告)号：US10977400B2

公开(公告)日：2021-04-13

申请号：US16548172

申请日：2019-08-22

申请人： Mentor Graphics Corporation

发明人： Wu-Tung Cheng ,  Kun-Han Tsai ,  Naixing Wang ,  Chen Wang ,  Xijiang Lin ,  Mark A. Kassab ,  Irith Pomeranz

IPC分类号： G06F30/30 ,  G06F119/12

摘要： Systems and methods for a deterministic automatic test generation (ATPG) process including Timing Exception ATPG (TEA). A method includes performing an automated test pattern generation (ATPG) process that uses timing exception information to generate a test pattern for a targeted fault of a circuit design with at least one timing exception path. The method includes testing the targeted fault of the circuit design using the test pattern to produce a test result for the targeted fault.

公开(公告)号：US09568552B2

公开(公告)日：2017-02-14

申请号：US14298663

申请日：2014-06-06

申请人： Mentor Graphics Corporation

发明人： Xijiang Lin ,  Janusz Rajski

IPC分类号： G01R31/28 ,  G01R31/3185 ,  G01R31/3183

CPC分类号： G01R31/318575 ,  G01R31/318385 ,  G01R31/318547

摘要： The test circuitry according to various aspects of the presently disclosed techniques comprises: low-toggling pseudo-random test pattern generation circuitry, wherein the low-toggling pseudo-random test patterns generated by the low-toggling pseudo-random test pattern generation circuitry causing switching activity during scan shift cycles lower than pseudo-random test patterns generated by a pseudo-random pattern generator; scan chains configurable to shift in a low-toggling pseudo-random test pattern generated by the low-toggling pseudo-random test pattern generation circuitry; background chains configurable to shift in a background test pattern; and weight insertion circuitry configurable to modify a plurality of bits in the low-toggling pseudo-random test pattern based on bits in the background test pattern to form a weighted pseudo-random test pattern.

摘要翻译： 根据当前公开的技术的各个方面的测试电路包括：低切换伪随机测试模式生成电路，其中由低切换伪随机测试模式产生电路产生的低切换伪随机测试模式引起切换 在扫描移位周期期间的活动低于由伪随机模式发生器产生的伪随机测试模式; 扫描链可配置为在由低切换伪随机测试图案生成电路产生的低切换伪随机测试图案中移位; 背景链可配置为在背景测试模式中移动; 以及加权插入电路，其可配置为基于所述背景测试图案中的比特来修改所述低切换伪随机测试模式中的多个比特，以形成加权的伪随机测试模式。