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公开(公告)号:US20120226891A1
公开(公告)日:2012-09-06
申请号:US13037830
申请日:2011-03-01
申请人: Michael D. ESTLICK , Jay FLEISCHMAN , Debjit Das Sarma , Emil TALPES , Krishnan V. RAMANI , Chun LIU
发明人: Michael D. ESTLICK , Jay FLEISCHMAN , Debjit Das Sarma , Emil TALPES , Krishnan V. RAMANI , Chun LIU
IPC分类号: G06F9/30
CPC分类号: G06F9/3861 , G06F9/30094 , G06F9/3842
摘要: Methods and apparatuses are provided for increased efficiency in a processor via control word prediction. The apparatus comprises an operational unit capable of determining whether an instruction will change a first control word to a second control word for processing dependent instructions. Execution units process the dependent instructions using a predicted control word and compare the second control word to the predicted control word. A scheduling unit causes the execution units to reprocess the dependent instructions when the predicted control word does not match the second control word. The method comprises determining that an instruction will change a first control word to a second control word and processing the dependent instructions using a predicted control word. The second control word is compared to the predicted control word and the dependent instructions are reprocessed using the second control word when the predicted control word does not match the second control word.
摘要翻译: 提供了通过控制字预测提高处理器效率的方法和装置。 该装置包括一个操作单元,其能够确定指令是否将第一控制字改变为第二控制字以用于处理相关指令。 执行单元使用预测的控制字处理依赖指令,并将第二控制字与预测的控制字进行比较。 当预测控制字与第二控制字不匹配时,调度单元使执行单元重新处理依赖指令。 该方法包括确定指令将第一控制字改变为第二控制字,并使用预测的控制字处理依赖指令。 将第二控制字与预测的控制字进行比较,并且当预测控制字与第二控制字不匹配时,使用第二控制字重新处理依赖指令。
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2.
公开(公告)号:US20120265966A1
公开(公告)日:2012-10-18
申请号:US13088096
申请日:2011-04-15
申请人: Michael D. ESTLICK , Kevin HURD , Jay FLEISCHMAN
发明人: Michael D. ESTLICK , Kevin HURD , Jay FLEISCHMAN
CPC分类号: G06F9/3855
摘要: Methods and apparatuses are provided for increased efficiency in a processor via early instruction completion. An apparatus is provided for increased efficiency in a processor via early instruction completion. The apparatus comprises an execution unit for processing instructions and determining whether a later issued instruction is ready for completion or an earlier issued instruction is ready for completion and a retire unit for retiring the later issued instruction when the later instruction is ready for completion or to retire the earlier instruction when later instruction is not ready for completion and the earlier issued instruction has a known good completion status. A method is provided for increased efficiency in a processor via early instruction completion. The method comprises completing an earlier issued instruction having a known good completion status ahead of a later issued instruction when the later issued instruction is not ready for completion.
摘要翻译: 提供了通过早期指令完成来提高处理器效率的方法和装置。 提供了一种通过早期指令完成来提高处理器的效率的装置。 该装置包括执行单元,用于处理指令并确定稍后发出的指令是否准备好完成,或者较早发出的指令准备好完成;以及退出单元,用于在稍后的指令准备完成或退出时退出稍后发出的指令 后期指令未准备好完成的早期指令,并且较早发出的指令具有已知的良好完成状态。 提供了一种通过早期指令完成来提高处理器的效率的方法。 该方法包括当稍后发出的指令未准备好完成时,完成先前发出的指令,该指令在稍后发出的指令之前具有已知的良好完成状态。
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公开(公告)号:US20120191952A1
公开(公告)日:2012-07-26
申请号:US13011637
申请日:2011-01-21
申请人: Jay E. FLEISCHMAN , Matthew M. CRUM , Kelvin GOVEAS , Michael D. ESTLICK , Barry J. ARNOLD , Ranganathan SUDHAKAR , Betty A. MCDANIEL
发明人: Jay E. FLEISCHMAN , Matthew M. CRUM , Kelvin GOVEAS , Michael D. ESTLICK , Barry J. ARNOLD , Ranganathan SUDHAKAR , Betty A. MCDANIEL
CPC分类号: G06F9/30094 , G06F9/30109 , G06F9/30192 , G06F9/384
摘要: Methods and apparatuses are provided for increased efficiency and enhanced power saving in a processor via scalar code optimization. The method comprises determining that an instruction comprises a scalar instruction and then processing the instruction using only a lower portion of an XMM register. The apparatus comprises an operational unit capable of determining whether an instruction comprises a scalar instruction and execution units responsive that determining for processing the scalar instruction using only a lower portion of an XMM register of the processor. By not processing the upper portion of the XMM register efficiency is increased and power saving is enhanced.
摘要翻译: 提供了通过标量代码优化在处理器中提高效率和增强功率节省的方法和装置。 该方法包括确定指令包括标量指令,然后仅使用XMM寄存器的下部来处理该指令。 所述装置包括能够确定指令是否包括标量指令的操作单元,并且所述执行单元响应于仅使用所述处理器的XMM寄存器的下部来确定所述标量指令的处理。 通过不处理XMM寄存器的上部部分,效率提高,省电。
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