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1.发明申请Method and Enhanced Phase Locked Loop Circuits for Implementing Effective Testing 审中-公开用于实现有效测试的方法和增强型锁相环电路公开(公告)号：US20080208541A1
公开(公告)日：2008-08-28
申请号：US11870159
申请日：2007-10-10
IPC分类号： G06F17/50
CPC分类号： G06F17/5063 , H03L7/18 , H03L7/1974
摘要： A method and enhanced phase-locked loop (PLL) circuit enable effective testing of the PLL, and a design structure on which the subject circuit resides is provided. A phase frequency detector generates a differential signal, receiving a reference signal and a feedback signal of an output signal of the PLL circuit. A charge pump is coupled to the phase frequency detector receiving the differential signal. The charge pump applies either negative or positive charge pulses to a low-pass filter, which generates a tuning voltage input applied to a voltage controlled oscillator. A first divider is coupled to the voltage controlled oscillator receives and divides down the VCO output signal, providing the output signal of the PLL circuit. A second divider receives the output signal of the PLL circuit and provides the feedback signal to the phase frequency detector. The output signal of PLL circuit is applied to a clock distribution.
摘要翻译： 一种方法和增强的锁相环（PLL）电路能够有效地测试PLL，并且提供主题电路所在的设计结构。 相位频率检测器产生差分信号，接收PLL电路的输出信号的参考信号和反馈信号。 电荷泵耦合到接收差分信号的相位频率检测器。 电荷泵将负电荷或正电荷脉冲施加到低通滤波器，产生施加到压控振荡器的调谐电压输入。 第一分频器耦合到压控振荡器接收并分频VCO输出信号，提供PLL电路的输出信号。 第二分频器接收PLL电路的输出信号，并将反馈信号提供给相位频率检测器。 PLL电路的输出信号应用于时钟分配。
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2.发明授权Method and enhanced phase locked loop circuits for implementing effective testing 失效用于实现有效测试的方法和增强锁相环电路公开(公告)号：US07538625B2
公开(公告)日：2009-05-26
申请号：US11679323
申请日：2007-02-27
CPC分类号： H03L7/1974 , G06F1/08
摘要： A method and enhanced phase-locked loop (PLL) circuit enable effective testing of the PLL. A phase frequency detector generates a differential signal, receiving a reference signal and a feedback signal of an output signal of the PLL circuit. A charge pump is coupled to the phase frequency detector receiving the differential signal. The charge pump applies either negative or positive charge pulses to a low-pass filter, which generates a tuning voltage input applied to a voltage controlled oscillator. A first divider is coupled to the voltage controlled oscillator receives and divides down the VCO output signal, providing the output signal of the PLL circuit. A second divider receives the output signal of the PLL circuit and provides the feedback signal to the phase frequency detector. The output signal of PLL circuit is applied to a clock distribution.
摘要翻译： 一种方法和增强型锁相环（PLL）电路能够有效地测试PLL。 相位频率检测器产生差分信号，接收PLL电路的输出信号的参考信号和反馈信号。 电荷泵耦合到接收差分信号的相位频率检测器。 电荷泵将负电荷或正电荷脉冲施加到低通滤波器，产生施加到压控振荡器的调谐电压输入。 第一分频器耦合到压控振荡器接收并分频VCO输出信号，提供PLL电路的输出信号。 第二分频器接收PLL电路的输出信号，并将反馈信号提供给相位频率检测器。 PLL电路的输出信号应用于时钟分配。
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3.发明申请Method and Enhanced Phase Locked Loop Circuits for Implementing Effective Testing 失效用于实现有效测试的方法和增强型锁相环电路公开(公告)号：US20080204154A1
公开(公告)日：2008-08-28
申请号：US11679323
申请日：2007-02-27
IPC分类号： H03J7/04
CPC分类号： H03L7/1974 , G06F1/08
摘要： A method and enhanced phase-locked loop (PLL) circuit enable effective testing of the PLL. A phase frequency detector generates a differential signal, receiving a reference signal and a feedback signal of an output signal of the PLL circuit. A charge pump is coupled to the phase frequency detector receiving the differential signal. The charge pump applies either negative or positive charge pulses to a low-pass filter, which generates a tuning voltage input applied to a voltage controlled oscillator. A first divider is coupled to the voltage controlled oscillator receives and divides down the VCO output signal, providing the output signal of the PLL circuit. A second divider receives the output signal of the PLL circuit and provides the feedback signal to the phase frequency detector. The output signal of PLL circuit is applied to a clock distribution.
摘要翻译： 一种方法和增强型锁相环（PLL）电路能够有效地测试PLL。 相位频率检测器产生差分信号，接收PLL电路的输出信号的参考信号和反馈信号。 电荷泵耦合到接收差分信号的相位频率检测器。 电荷泵将负电荷或正电荷脉冲施加到低通滤波器，产生施加到压控振荡器的调谐电压输入。 第一分频器耦合到压控振荡器接收并分频VCO输出信号，提供PLL电路的输出信号。 第二分频器接收PLL电路的输出信号，并将反馈信号提供给相位频率检测器。 PLL电路的输出信号应用于时钟分配。
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