公开(公告)号：US07760843B2

公开(公告)日：2010-07-20

申请号：US12187517

申请日：2008-08-07

Applicant: David William Boerstler ,  Eric John Lukes ,  Hiroki Kihara ,  James David Strom

Inventor： David William Boerstler ,  Eric John Lukes ,  Hiroki Kihara ,  James David Strom

IPC: H03K21/00

CPC classification number: H03K21/406 ,  G06F7/58

Abstract: The present invention provides for a self-correcting state circuit. A first flip flop is configured to receive a clock input and a first data input, and to generate a first output in response to the clock input and the first data input. A second flip flop is coupled to the first flip flop and configured to receive the clock input and to receive the first output as a second data input, and to generate a second output in response to the clock input and the first output. A first correction circuit is coupled to the second flip flop and configured to generate a corrected output. A third flip flop is coupled to the first correction circuit and configured to receive the clock input and to receive the corrected output as a third data input, and to generate a third output in response to the clock input and the third data input.

Abstract translation: 本发明提供一种自校正状态电路。 第一触发器被配置为接收时钟输入和第一数据输入，并且响应于时钟输入和第一数据输入而产生第一输出。 第二触发器耦合到第一触发器并且被配置为接收时钟输入并且接收第一输出作为第二数据输入，并且响应于时钟输入和第一输出而产生第二输出。 第一校正电路耦合到第二触发器并且被配置为产生校正输出。 第三触发器耦合到第一校正电路并且被配置为接收时钟输入并且接收校正的输出作为第三数据输入，并且响应于时钟输入和第三数据输入而产生第三输出。

公开(公告)号：US20080208541A1

公开(公告)日：2008-08-28

申请号：US11870159

申请日：2007-10-10

Applicant: Michael David Cesky ,  James David Strom

Inventor： Michael David Cesky ,  James David Strom

IPC: G06F17/50

CPC classification number: G06F17/5063 ,  H03L7/18 ,  H03L7/1974

Abstract: A method and enhanced phase-locked loop (PLL) circuit enable effective testing of the PLL, and a design structure on which the subject circuit resides is provided. A phase frequency detector generates a differential signal, receiving a reference signal and a feedback signal of an output signal of the PLL circuit. A charge pump is coupled to the phase frequency detector receiving the differential signal. The charge pump applies either negative or positive charge pulses to a low-pass filter, which generates a tuning voltage input applied to a voltage controlled oscillator. A first divider is coupled to the voltage controlled oscillator receives and divides down the VCO output signal, providing the output signal of the PLL circuit. A second divider receives the output signal of the PLL circuit and provides the feedback signal to the phase frequency detector. The output signal of PLL circuit is applied to a clock distribution.

Abstract translation: 一种方法和增强的锁相环（PLL）电路能够有效地测试PLL，并且提供主题电路所在的设计结构。 相位频率检测器产生差分信号，接收PLL电路的输出信号的参考信号和反馈信号。 电荷泵耦合到接收差分信号的相位频率检测器。 电荷泵将负电荷或正电荷脉冲施加到低通滤波器，产生施加到压控振荡器的调谐电压输入。 第一分频器耦合到压控振荡器接收并分频VCO输出信号，提供PLL电路的输出信号。 第二分频器接收PLL电路的输出信号，并将反馈信号提供给相位频率检测器。 PLL电路的输出信号应用于时钟分配。

公开(公告)号：US06239665B1

公开(公告)日：2001-05-29

申请号：US09432673

申请日：1999-11-02

Applicant: James David Strom

Inventor： James David Strom

IPC: H03B508

CPC classification number: H03B5/1228 ,  H03B5/1215 ,  H03B5/1253 ,  H03B5/1265 ,  H03J2200/10

Abstract: A method and apparatus are provided for switching in metal insulator metal (MIM) capacitors and field effect transistor (FET) tuning capacitors for oscillator circuits. Apparatus for switching in metal-insulator-metal (MIM) capacitors and field effect transistor (FET) tuning capacitors for oscillator circuits includes a first differential oscillator node and a second differential oscillator node. A plurality of metal-insulator-metal (MIM) capacitors are connected to the first differential oscillator nodes and a plurality of metal-insulator-metal (MIM) capacitors are connected to the second differential oscillator nodes. A respective switching transistor is connected in series with an associated one of the metal-insulator-metal (MIM) capacitors. Each switching transistor receives a decoding input and is arranged for providing an open or a ground connection for the associated one of the metal-insulator-metal (MIM) capacitors. A first field effect transistor (FET) tuning capacitor has a gate connected to the first differential oscillator node. A second field effect transistor (FET) tuning capacitor has a gate connected to the second differential oscillator node. Each of the first field effect transistor (FET) tuning capacitor and the second field effect transistor (FET) tuning capacitor having a source and a drain connected together and a control voltage applied to the connected source and drain for varying tuning capacitance.

Abstract translation: 提供了用于切换用于振荡器电路的金属绝缘体金属（MIM）电容器和场效应晶体管（FET）调谐电容器的方法和装置。 用于切换用于振荡器电路的金属 - 绝缘体金属（MIM）电容器和场效应晶体管（FET）调谐电容器的装置包括第一差分振荡器节点和第二差分振荡器节点。 多个金属绝缘体金属（MIM）电容器连接到第一差分振荡器节点，并且多个金属 - 绝缘体金属（MIM）电容器连接到第二差分振荡器节点。 相应的开关晶体管与金属 - 绝缘体 - 金属（MIM）电容器中的相关联的一个串联连接。 每个开关晶体管接收解码输入，并且被布置成为金属 - 绝缘体 - 金属（MIM）电容器中相关联的一个提供开路或接地连接。 第一场效应晶体管（FET）调谐电容器具有连接到第一差分振荡器节点的栅极。 第二场效应晶体管（FET）调谐电容器具有连接到第二差分振荡器节点的栅极。 第一场效应晶体管（FET）调谐电容器和具有连接在一起的源极和漏极的第二场效应晶体管（FET）调谐电容器以及施加到所连接的源极和漏极的控制电压用于改变调谐电容。

公开(公告)号：US5903195A

公开(公告)日：1999-05-11

申请号：US16848

申请日：1998-01-30

Applicant: Eric John Lukes ,  James David Strom ,  Dana Marie Woeste

Inventor： Eric John Lukes ,  James David Strom ,  Dana Marie Woeste

IPC: H03L7/095 ,  H03L7/099 ,  H03L7/10 ,  H03L7/12

CPC classification number: H03L7/095 ,  H03L7/0995 ,  H03L7/10 ,  Y10S331/02

Abstract: An improved phase locked loop (PLL) circuit is provided for use in microprocessor clock generation. A ring oscillator provides an output frequency signal. A voltage to current converter converts differential control voltages to a variable reference current applied to the ring oscillator. A range control reference current generator applies a range control reference current to the ring oscillator. A range control operatively controls the range control reference current generator to sequentially change the range control reference current applied to the ring oscillator. A lock detector coupled to the range control compares the output frequency signal and a reference frequency signal and responsive to the compares signals applies a locked signal to the range control. Responsive to an applied locked signal, the range control stops changing ranges. The phase locked loop (PLL) circuit automatically sweeps through multiple frequency subranges responsive to the range control. A control signal is applied to the voltage to current converter for selectively controlling an operational mode of the voltage to current converter from a squelched operational mode to an unsquelched operational mode after a set time period. This control signal also is applied to the range control, so that the range control stops changing ranges.

Abstract translation: 提供改进的锁相环（PLL）电路用于微处理器时钟产生。 环形振荡器提供输出频率信号。 电压 - 电流转换器将差分控制电压转换为施加到环形振荡器的可变参考电流。 范围控制参考电流发生器将范围控制参考电流施加到环形振荡器。 范围控制可操作地控制距离控制参考电流发生器以顺序地改变施加到环形振荡器的范围控制参考电流。 耦合到量程控制的锁定检测器比较输出频率信号和参考频率信号，并且响应于比较信号将锁定信号施加到范围控制。 响应于所施加的锁定信号，范围控制停止变化范围。 锁相环（PLL）电路根据范围控制自动扫描多个频率子范围。 控制信号被施加到电压到电流转换器，用于在设定的时间段之后选择性地将电压/电流转换器的操作模式从压缩操作模式控制到未校准的操作模式。 该控制信号也适用于量程控制，使范围控制停止变化范围。

公开(公告)号：US07173482B2

公开(公告)日：2007-02-06

申请号：US11094711

申请日：2005-03-30

Applicant: Katherine Ellen Lobb ,  Patrick Lee Rosno ,  James David Strom

Inventor： Katherine Ellen Lobb ,  Patrick Lee Rosno ,  James David Strom

IPC: G05F1/10

CPC classification number: G05F3/242

Abstract: A complementary metal oxide semiconductor (CMOS) voltage regulator for low headroom applications includes a differential input common mode range amplifier. The differential input common mode range amplifier is formed by a plurality of CMOS transistors. A source follower CMOS transistor is coupled to an output of the differential input common mode range amplifier for providing an output of the CMOS voltage regulator. A current source is coupled to the differential input common mode range amplifier for maintaining a bias current through the differential input common mode range amplifier.

Abstract translation: 用于低余量应用的互补金属氧化物半导体（CMOS）电压调节器包括差分输入共模范围放大器。 差分输入共模范围放大器由多个CMOS晶体管形成。 源极跟随器CMOS晶体管耦合到差分输入共模范围放大器的输出，用于提供CMOS电压调节器的输出。 电流源耦合到差分输入共模范围放大器，用于保持偏置电流通过差分输入共模范围放大器。

公开(公告)号：US06670655B2

公开(公告)日：2003-12-30

申请号：US09837839

申请日：2001-04-18

Applicant: Eric John Lukes ,  Patrick Lee Rosno ,  James David Strom

Inventor： Eric John Lukes ,  Patrick Lee Rosno ,  James David Strom

IPC: H01L27148

CPC classification number: H01L27/1203 ,  H01L29/783

Abstract: A method and apparatus are provided for implementing a body contact in a silicon-on-insulator field effect transistor device. A SOI field effect transistor is provided having a body contact having a predefined resistance that provides a higher device threshold voltage in the SOI FET device. A body of the SOI field effect transistor is connected to the gate of the SOI field effect transistor. The body gate connection of the SOI field effect transistor effectively lowers the device threshold voltage due to body bias effect. The SOI field effect transistor with a body connected to the gate of the SOI field effect transistor is used in circuits having stacked devices and DC currents. The SOI field effect transistor with a body connected to the gate of the SOI field effect transistor also is used in analog circuits with device matching requirements and in circuits having a low voltage power supply.

公开(公告)号：US06342793B1

公开(公告)日：2002-01-29

申请号：US09433394

申请日：1999-11-03

Applicant: Eric John Lukes ,  James David Strom ,  Dana Marie Woeste

Inventor： Eric John Lukes ,  James David Strom ,  Dana Marie Woeste

IPC: H03K190175

CPC classification number: H03K19/00346 ,  H03K19/017563

Abstract: A CMOS signal transmission system for sending a large amount of CMOS signals into a separate quiet analog power domain. Transmission system comprises a converter sub-system which provides at least another device stage through which noise in the CMOS signals must flow and be attenuated to provide converted CMOS signals and a multiplexer coupled to the converter wherein the multiplexer receives converted CMOS signals from the converter sub-system and also receives delayed path control signals. The converter comprises a constant current source for providing a high level voltage reference and a constant current, two complimentary pass gates, and two sets of components for providing paths to ground from the constant current source through the two complimentary pass gates. When CMOS input signal is high and Complimentary CMOS input signal is low, the pass gate comprising transistors T9 and T1 is on and transistors T8 and T0 are off and connection BSEL is pulled high turning on bipolar transistor Q9 allowing current to flow through Q9 and pulling net SB low and selecting inputs B0, B1 to be transferred to ECL Differential Outputs. Likewise, when CMOS input signal is low and Complimentary CMOS input signal is high, pass gate comprising transistors T8 and T0 is on, and transistors T9 and T1 are off, and connection ASEL is pulled high turning on bipolar transistor Q8 allowing current to flow through Q8 and pulling net SA low and selecting inputs A0, A1 to be transferred to ECL Differential Outputs.

Abstract translation: CMOS信号传输系统，用于将大量的CMOS信号发送到独立的静态模拟电源域。 传输系统包括转换器子系统，其提供至少另一个器件级，CMOS信号中的噪声必须通过该器件级流动并被衰减以提供转换的CMOS信号;以及耦合到转换器的多路复用器，其中多路复用器从转换器子接收转换的CMOS信号 并且还接收延迟路径控制信号。 该转换器包括用于提供高电平电压基准的恒流源和恒定电流两个互补栅极，以及用于通过两个互补栅极从恒定电流源提供到地的路径的两组元件。 当CMOS输入信号为高电平且免费CMOS输入信号为低电平时，包括晶体管T9和T1的通过栅导通，晶体管T8和T0断开，并连接BSEL被拉高，双极晶体管Q9导通，允许电流流过Q9并拉动 净SB低，并选择输入B0，B1传输到ECL差分输出。 同样地，当CMOS输入信号为低电平，并且免费CMOS输入信号为高电平时，包括晶体管T8和T0的通路导通，晶体管T9和T1截止，并且连接ASEL被拉高，导通双极晶体管Q8，允许电流流过 Q8和拉低SA SA，并选择输入A0，A1传输到ECL差分输出。

公开(公告)号：US06232806B1

公开(公告)日：2001-05-15

申请号：US09177142

申请日：1998-10-21

Applicant: Dana Marie Woeste ,  James David Strom ,  Bruce George Rudolph

Inventor： Dana Marie Woeste ,  James David Strom ,  Bruce George Rudolph

IPC: H03K706

CPC classification number: G06F1/10 ,  H03K5/133 ,  H03L7/07 ,  H03L7/0814

Abstract: An apparatus and method for distributing a clock signal within circuitry disposed on a number of separate system cards includes a first system card that generates a reference clock signal representative of a fixed delay of a system clock signal. A number of variable clock signals are produced using the system clock signal. Each of a number of system cards separate from the first system card receive one of the variable clock signals. A delay associated with the reference clock signal is typically longer than a delay associated with each of the variable clock signals. The phase of each of the variable clock signals is adjusted to a substantially in-phase relationship with respect to the reference clock signal in response to a phase difference between the reference clock signal an output signal received from each of the separate system cards. Producing each of the variable clock signals may involve selecting between a first delay line and a second delay line, and then producing the variable delay signal using the selected first or second delay line. A delay factor of the non-selected first or second delay line may be changed by varying a resistance and a current of one or more delay elements of the non-selected first or second delay lines. The circuitry is selectably operable in a slave or buffer-type clock repowering mode or an adaptive mode. The variable clock signals and the output signals may respectively comprise low voltage differential signals (LVDS) or CMOS level signals.

Abstract translation: 一种用于在设置在多个单独的系统卡上的电路内分配时钟信号的装置和方法包括产生表示系统时钟信号的固定延迟的参考时钟信号的第一系统卡。 使用系统时钟信号产生多个可变时钟信号。 与第一系统卡分开的多个系统卡中的每一个都接收可变时钟信号之一。 与参考时钟信号相关联的延迟通常比与每个可变时钟信号相关联的延迟更长。 每个可变时钟信号的相位响应于参考时钟信号从每个单独的系统卡接收的输出信号之间的相位差而相对于参考时钟信号被调整到基本上同相的关系。 产生每个可变时钟信号可以包括在第一延迟线和第二延迟线之间进行选择，然后使用所选择的第一或第二延迟线产生可变延迟信号。 可以通过改变未选择的第一或第二延迟线的一个或多个延迟元件的电阻和电流来改变未选择的第一或第二延迟线的延迟因子。 电路可选择地以从属或缓冲型时钟重新供电模式或自适应模式工作。 可变时钟信号和输出信号可以分别包括低电压差分信号（LVDS）或CMOS电平信号。

公开(公告)号：US5831484A

公开(公告)日：1998-11-03

申请号：US826436

申请日：1997-03-18

Applicant: Eric John Lukes ,  James David Strom

Inventor： Eric John Lukes ,  James David Strom

IPC: H03L7/089

CPC classification number: H03L7/0895 ,  H03L7/0896

Abstract: A differential charge pump is provided for use with phase locked loop (PLL) circuits including a differential loop filter and a common mode bias circuit for maintaining a predetermined bias voltage value on a high voltage filter side of the loop filter. The differential charge pump includes a reference current source. First and second current mirrors are coupled to the reference current source for providing a first mirror current and a second mirror current. A first switching transistor coupled to the first current mirror receives an input UP signal conducts current from a first side of the loop filter. A second switching transistor coupled to the second current mirror receives an input DOWN signal and conducts current from a second side of the loop filter. The first and second current mirror and switching transistors are formed by N-channel metal oxide semiconductor (NMOS) devices. The differential charge pump enables a large differential output voltage with low phase error.

Abstract translation: 提供差分电荷泵用于包括差分环路滤波器和共模偏置电路的锁相环（PLL）电路，用于在环路滤波器的高电压滤波器侧上保持预定的偏置电压值。 差分电荷泵包括参考电流源。 第一和第二电流镜耦合到参考电流源，以提供第一反射镜电流和第二反射镜电流。 耦合到第一电流镜的第一开关晶体管接收输入UP信号从环路滤波器的第一侧传导电流。 耦合到第二电流镜的第二开关晶体管接收输入的DOWN信号，并且从环路滤波器的第二侧传导电流。 第一和第二电流镜和开关晶体管由N沟道金属氧化物半导体（NMOS）器件形成。 差分电荷泵能够实现具有低相位误差的大差分输出电压。

公开(公告)号：US5815694A

公开(公告)日：1998-09-29

申请号：US576172

申请日：1995-12-21

Applicant: Paul Allen Ganfield ,  Charles Luther Johnson ,  James David Strom

Inventor： Paul Allen Ganfield ,  Charles Luther Johnson ,  James David Strom

IPC: G06F1/08

CPC classification number: G06F1/08

Abstract: An apparatus and method for providing a variable frequency clock source is described wherein the frequency may be changed while maintaining the phase of the clock signal. A frequency conversation circuit, such as a phase locked loop (PLL), is employed to change the frequency of the clock and is controlled by a control unit which maintains the phase of the output clock signal while undergoing a frequency change operation.

Abstract translation: 描述了一种用于提供可变频率时钟源的装置和方法，其中可以在保持时钟信号的相位的同时改变频率。 使用诸如锁相环（PLL）的频率对话电路来改变时钟的频率，并且由控制单元控制，该控制单元在经历频率改变操作时保持输出时钟信号的相位。