-
公开(公告)号：US07027064B2
公开(公告)日：2006-04-11
申请号：US10086174
申请日：2002-02-28
CPC分类号： G09G5/39 , G06F12/0804 , G06F12/0897 , G06F12/126 , G06F2212/455 , G06T1/60 , G09G2360/121
摘要： An external cache management unit for use with 3D-RAM and suitable for use in a computer graphics system is described. The unit maintains and tracks the status of level one cache memory in the 3D-RAM. The unit identifies dirty blocks of cache memory and prioritizes block cleansing based on a least used algorithm. Periodic block cleansing during empty memory cycles is provided for, and may also be prompted on demand.
-
公开(公告)号：US06847369B2
公开(公告)日：2005-01-25
申请号：US10060915
申请日：2002-01-30
摘要： A data queue optimized for receiving loosely packed graphics data and suitable for use in a computer graphics system is described. The data queue operates on first-in-first-out principals, and has a variable width input and output. The variable width on the input side facilitates the reception and storage of loosely packed data. The variable width output allows for the single-cycle output of multi-word data. Packing of the data occurs on the write-side of the FIFO structure.
摘要翻译： 描述了优化用于接收松散封装的图形数据并适合于在计算机图形系统中使用的数据队列。 数据队列以先进先出原则进行操作，并具有可变宽度的输入和输出。 输入侧的可变宽度有助于松散打包数据的接收和存储。 可变宽度输出允许多字数据的单周期输出。 数据的包装发生在FIFO结构的写入端。
-
3.发明授权Early primitive assembly and screen-space culling for multiple chip graphics system 有权早期的原始装配和屏幕空间剔除多芯片图形系统公开(公告)号：US06943797B2
公开(公告)日：2005-09-13
申请号：US10611271
申请日：2003-06-30
CPC分类号： G06T15/005 , G06T1/60 , H04N19/42 , H04N19/80
摘要： A multi-chip system and method are disclosed for incorporating a primitive assembler in each of one or more geometry chips and one or more rasterization chips. This system may allow per-primitive operations to be performed in the geometry chips, and also allow use of a vertex data interface for sending vertex data to the rasterization chips. The primitive assemblers in the geometry chips may assemble vertices into primitives for clipping tests. The geometry chips may also test an assembled primitive against the projected boundaries of a set of screen space regions, where each region is assigned to one of the rasterization chips. Those primitives residing in more than one region may be sub-divided into two or more new primitives so that each new primitive resides in only one screen space region. The geometry chip may then send the vertex data for each primitive to the corresponding rasterization chip.
摘要翻译： 公开了一种用于将原始汇编器并入一个或多个几何码片和一个或多个光栅化码片的每一个中的多芯片系统和方法。 该系统可以允许在几何芯片中执行每个原始操作，并且还允许使用顶点数据接口将顶点数据发送到光栅化芯片。 几何芯片中的原始汇编器可以将顶点组装成用于剪切测试的基元。 几何芯片还可以针对一组屏幕空间区域的投影边界来测试组合的图元，其中每个区域被分配给光栅化芯片中的一个。 驻留在多个区域中的这些原语可以被细分为两个或更多个新的基元，使得每个新的基元仅驻留在一个屏幕空间区域。 然后，几何芯片可以将每个基元的顶点数据发送到相应的光栅化芯片。
-
4.发明授权公开(公告)号：US06859209B2
公开(公告)日：2005-02-22
申请号：US09861468
申请日：2001-05-18
申请人： Michael G. Lavelle , Brian D. Emberling , Ranjit S. Oberoi , Deron D. Johnson , Ewa M. Kubalska
发明人： Michael G. Lavelle , Brian D. Emberling , Ranjit S. Oberoi , Deron D. Johnson , Ewa M. Kubalska
CPC分类号： G09G5/363 , G06T11/40 , G06T15/005
摘要： A graphics system applies multiple layers of texture information to triangles. The graphics system includes a hardware accelerator, a frame buffer and a video output processor. The hardware accelerator receives vertices of a triangle, identifies fragments of a sampling space which intersect the triangle, and applies the multiple layers of texture to the intersecting fragments. The multiple layers of textures may be stored in a texture memory external to the hardware accelerator. The hardware accelerator switches to a next texture layer after applying the textures of a current layer to all the fragments of the triangle. The hardware accelerator includes (or couples to) a texture accumulation buffer which stores color values associated with the triangle fragments between the application of successive texture layers. The frame buffer stores the samples and pixels generated from the samples by filtration. The video output processor transforms the pixels into a video signal.
摘要翻译： 图形系统将多层纹理信息应用于三角形。 图形系统包括硬件加速器，帧缓冲器和视频输出处理器。 硬件加速器接收三角形的顶点，识别与三角形相交的采样空间的片段，并将多层纹理应用于相交片段。 多层纹理可以存储在硬件加速器外部的纹理存储器中。 硬件加速器在将当前层的纹理应用于三角形的所有片段之后切换到下一个纹理层。 硬件加速器包括（或耦合到）纹理累积缓冲器，其存储与连续纹理层的应用之间的三角形片段相关联的颜色值。 帧缓冲器通过过滤存储从样本产生的样本和像素。 视频输出处理器将像素转换为视频信号。
-
5.发明授权Rasterization using two-dimensional tiles and alternating bins for improved rendering utilization 有权使用二维瓦片和交替箱体进行光栅化，以提高渲染利用率公开(公告)号：US06803916B2
公开(公告)日：2004-10-12
申请号：US09861475
申请日：2001-05-18
申请人： Nandini Ramani , David C. Kehlet , Ewa M. Kubalska , Michael G. Lavelle , Michael A. Wasserman , Kevin Tang , Yan Yan Tang
发明人： Nandini Ramani , David C. Kehlet , Ewa M. Kubalska , Michael G. Lavelle , Michael A. Wasserman , Kevin Tang , Yan Yan Tang
IPC分类号： G06T120
摘要： A system and method for rasterizing and rendering graphics data is disclosed. Vertices may be grouped to form primitives such as triangles, which are rasterized using two-dimensional arrays of samples bins. Individual samples may be selected from the bins according to different criteria such as memory bank allocation to improve utilization of the system's rendering pipeline. Since the arrays may have more bins than the number of evaluation units in the rendering pipeline, the samples from the bins may be stored to FIFO memories to allow invalid or empty samples (those outside the primitive being rendered) to be removed. The samples may then be filtered to form pixels that are displayable to form an image on a display device.
摘要翻译： 公开了一种用于光栅化和渲染图形数据的系统和方法。 顶点可以被分组以形成诸如三角形的图元，其使用样本仓的二维阵列进行光栅化。 可以根据诸如存储体分配的不同标准从箱中选择单个样本，以提高系统的渲染管线的利用率。 由于阵列可以具有比渲染流水线中的评估单元数更多的存储单元，所以来自存储区的样本可以被存储到FIFO存储器中以允许去除无效或空的样本（被渲染的原始图像之外的样本）。 然后可以对样本进行滤波以形成可显示以在显示装置上形成图像的像素。
-
公开(公告)号：US06781406B2
公开(公告)日：2004-08-24
申请号：US10090481
申请日：2002-03-04
IPC分类号： H03K19173
CPC分类号： G01R31/318516 , G01R31/31705 , G01R31/3172 , G01R31/31722 , G01R31/31723
摘要： An integrated circuit including logic for testing internal operation of the integrated circuit. The integrated circuit may comprise a plurality of internal functional blocks coupled by a plurality of internal buses. The integrated circuit may also comprise a set of test control input pins and a set of test output pins comprised on the integrated circuit. The integrated circuit may comprise selection logic. The selection logic comprises inputs coupled to various ones of the internal buses, an output coupled to the set of test output pins, and a select input coupled to receive select signals from the set of test control input pins. The selection logic is operable to select internal bus signals from an internal bus based on the select signals from the test control input pins, and the selection logic is configured to output the selected internal bus signals to the set of test output pins. The integrated circuit thus allows multiplexing of different critical internal buses so that the signals on the critical buses may be output for observation via selected test pins on the integrated circuit. The observability logic may be configured to switch slowly relative to the internal busses, and the generation of the observability logic and testing may be automated.
摘要翻译： 一种集成电路，包括用于测试集成电路的内部操作的逻辑。 集成电路可以包括通过多个内部总线耦合的多个内部功能块。 集成电路还可以包括一组测试控制输入引脚和一组包含在集成电路上的测试输出引脚。 集成电路可以包括选择逻辑。 选择逻辑包括耦合到各种内部总线的输入，耦合到该组测试输出引脚的输出以及耦合以从该组测试控制输入引脚接收选择信号的选择输入。 选择逻辑可操作以基于来自测试控制输入引脚的选择信号从内部总线选择内部总线信号，并且选择逻辑被配置为将所选择的内部总线信号输出到测试输出引脚组。 因此，集成电路允许复用不同的关键内部总线，使得可以输出关键总线上的信号，以便通过集成电路上的选定测试引脚进行观察。 可观测性逻辑可以被配置为相对于内部总线缓慢地切换，并且可观察性逻辑和测试的产生可以是自动化的。
-
公开(公告)号：US06778179B2
公开(公告)日：2004-08-17
申请号：US09970113
申请日：2001-10-03
IPC分类号： G09G536
CPC分类号： G06F12/0897 , G06T1/60 , G06T15/005 , G09G5/363 , G09G5/39 , G09G2360/121 , G09G2360/122 , Y02D10/13
摘要： An external cache management unit for use with a 3D-RAM frame buffer and suitable for use in a computer graphics system is described. The unit may reduce power consumption within the 3D-RAM by performing partial block write-back according to status information stored in an array of dirty tag bits. Periodic level one cache block cleansing is provided for during empty memory cycles.
摘要翻译： 描述了一种用于3D-RAM帧缓冲器并适用于计算机图形系统的外部高速缓存管理单元。 该单元可以通过根据存储在脏标签位阵列中的状态信息执行部分块回写来减少3D-RAM内的功耗。 在空的存储器循环期间提供了周期性的一级缓存块清理。
-
8.发明授权Program sequencer for generating indeterminant length shader programs for a graphics processor 有权用于为图形处理器生成不确定长度着色器程序的程序定序器公开(公告)号：US08659601B1
公开(公告)日：2014-02-25
申请号：US11893404
申请日：2007-08-15
CPC分类号： G06T15/005 , G06F9/5083 , G06T1/20
摘要： A method for loading and executing an indeterminate length shader program. The method includes accessing a first portion of a shader program in graphics memory of a GPU and loading instructions from the first portion into a plurality of stages of the GPU to configure the GPU for program execution. A group of pixels is then processed in accordance with the instructions from the first portion. A second portion of the shader program is accessed in graphics memory of the GPU and instructions from the second portion are loaded into the plurality of stages of the GPU to configure the GPU for program execution. The group of pixels are then processed in accordance with the instructions from the second portion.
摘要翻译： 一种用于加载和执行不确定长度着色器程序的方法。 该方法包括访问GPU的图形存储器中的着色器程序的第一部分，并且将指令从第一部分加载到GPU的多个阶段以配置GPU用于程序执行。 然后根据来自第一部分的指令对一组像素进行处理。 在GPU的图形存储器中访问着色器程序的第二部分，并且来自第二部分的指令被加载到GPU的多个级中以配置GPU用于程序执行。 然后根据来自第二部分的指令对像素组进行处理。
-
9.发明授权Large-kernel convolution using multiple industry-standard graphics accelerators 有权使用多个行业标准图形加速器的大内核卷积公开(公告)号：US07737994B1
公开(公告)日：2010-06-15
申请号：US10673088
申请日：2003-09-26
申请人： Michael A. Wasserman , Ewa M. Kubalska , Nathaniel David Naegle , Brian D. Emberling , Paul R. Ramsey , Mark E. Pascual
发明人： Michael A. Wasserman , Ewa M. Kubalska , Nathaniel David Naegle , Brian D. Emberling , Paul R. Ramsey , Mark E. Pascual
CPC分类号： G06T11/40 , G06T1/20 , G09G5/14 , G09G5/363 , G09G2360/06 , G09G2360/121 , G09G2360/18
摘要： A multi-chip system and method are disclosed that utilizes a plurality of graphics pipelines to perform large kernel convolution. Each graphics pipeline includes a standard rendering unit and a video data convolve unit. Each video data convolve unit receives video pixel data from the video output of the standard rendering unit. The video data convolve units are connected in a chain. Each group of one or more video data convolve units in the chain convolves the video pixel data received by the group. The last video data convolve unit in the chain outputs a stream of convolved pixels.
摘要翻译： 公开了利用多个图形管线来执行大的内核卷积的多芯片系统和方法。 每个图形流水线包括标准渲染单元和视频数据卷积单元。 每个视频数据卷积单元从标准渲染单元的视频输出接收视频像素数据。 视频数据卷积单元连接在一起。 链中的每一组一个或多个视频数据卷积单元卷积由该组接收的视频像素数据。 链中的最后一个视频数据卷积单元输出一个卷积像素流。
-
公开(公告)号：US06833834B2
公开(公告)日：2004-12-21
申请号：US10021096
申请日：2001-12-12
IPC分类号： G06F1300
CPC分类号： G09G3/006 , G06F3/1431 , G09G5/001 , G09G5/18 , G09G5/363 , G09G5/395 , G09G2360/123
摘要： A graphics system includes a frame buffer, a write address generator, and a pixel buffer. A burst of pixels received from the frame buffer may not be in display order. In one embodiment, a write address generator calculates a write address for each pixel in the burst of pixels output from the frame buffer. The write address corresponds to a relative display order within the burst for each respective pixel. Each pixel in the burst is stored to its write address in the pixel buffer. This way, the pixels in the burst are stored in display order within the pixel buffer.
摘要翻译： 图形系统包括帧缓冲器，写地址生成器和像素缓冲器。 从帧缓冲器接收到的像素突发可能不是显示顺序。 在一个实施例中，写地址生成器计算从帧缓冲器输出的像素突发中的每个像素的写入地址。 写入地址对应于每个相应像素的突发内的相对显示顺序。 突发中的每个像素被存储到像素缓冲器中的其写入地址。 这样，突发中的像素以像素缓冲器内的显示顺序存储。
-
-
-
-
-
-
-
-
-
搜索结果
23 条记录 (耗时 0.023 秒)
