摘要:
A mechanism is provided for gating a read access of any row in a cache access memory that has been invalidated. An address decoder in the cache access memory sends a memory access to a non-gated wordline driver and a gated wordline driver associated with the memory access. The non-gated wordline driver outputs the data stored in a valid bit memory cell to the gated wordline driver in response to the non-gated wordline driver determining the memory access as a read access. The gated wordline driver determines whether the data from the valid bit memory cell from the non-gated wordline driver indicates either valid data or invalid data in response to the gated wordline driver determining the memory access as a read access and denies an output of the data in a row of memory cells associated with the gated wordline driver in response to the data being invalid.
摘要:
A mechanism for reducing the amount of power or energy consumed by an SRAM array when the SRAM array is being accessed is provided. Logic is provided that identifies a polarity of a row of memory cells whose data values are to be read. The polarity of the row of memory cells indicates whether a majority of the data values stored in the row of memory cells are logic 1 data values or logic 0 data values. Based on the polarity, selection logic either selects true data values or complement data values of the memory cells. Additional logic is provided in each memory cell for outputting a true data value to a read bit line and outputting a compliment data value to the read bit line based on the polarity.
摘要:
A mechanism for reducing the amount of power or energy consumed by an SRAM array when the SRAM array is being accessed are provided. Logic is provided for determining the polarity of an incoming row being written to the SRAM cell array. Logic is further provided for storing a polarity value into an additional SRAM cell per row of the SRAM cell array. Logic is also provided for reading an inverted value of the SRAM cells of a row in the SRAM cell array if the row contains more 0's than 1's, as determined based on the polarity value stored in the additional SRAM cell per row. Logic is further provided for signaling to downstream logic whether the data read from the SRAM cells in the row represents the true data values or their complement, as determined based on the polarity value stored in the additional SRAM cell per row.
摘要:
A mechanism is provided for enabling a proper write through during a write-through operation. Responsive to determining the memory access as a write-through operation, first circuitry determines whether a data input signal is in a first state or a second state. Responsive to the data input signal being in the second state, the first circuitry outputs a global write line signal in the first state. Responsive to the global write line signal being in the first state, second circuitry outputs a column select signal in the second state. Responsive to the column select signal being in the second state, third circuitry keeps a downstream read path of the cache access memory at the first state such that data output by the cache memory array is in the first state.
摘要:
An apparatus and method for transparent multi-hit correction in associative memories are provided. In one illustrative embodiment, a content associative memory (CAM) device is provided that transparently and independently executes a precise corrective action in the case of a multiple hit being detected. The wordlines of a CAM array are modified to include a valid bit storage circuit element that indicates whether or not the corresponding wordline is valid or not. In operation, if multiple hits are detected, the multiple hit is signaled to the host system and the particular entries in the CAM array corresponding to the multiple hits are invalidated by setting their associated valid bit storage circuit elements to an invalid value or clearing the value in the associated valid bit storage circuit element. Any data returned to the host system as a result of the multiple hits is invalidated in the host system in response to the signaling of the multiple hits.
摘要:
A mechanism is provided for gating a read access of any row in a cache access memory that has been invalidated. An address decoder in the cache access memory sends a memory access to a non-gated wordline driver and a gated wordline driver associated with the memory access. The non-gated wordline driver outputs the data stored in a valid bit memory cell to the gated wordline driver in response to the non-gated wordline driver determining the memory access as a read access. The gated wordline driver determines whether the data from the valid bit memory cell from the non-gated wordline driver indicates either valid data or invalid data in response to the gated wordline driver determining the memory access as a read access and denies an output of the data in a row of memory cells associated with the gated wordline driver in response to the data being invalid.
摘要:
Mechanisms for multiple hit (multi-hit) detection in associative memories, such as a content addressable memory (CAM), are provided. The illustrative embodiments include a hit bitline that discharges as RAM side entries of the associative memory are accessed. The hit bitline is precharged high and pulled low by a series of devices that are activated as each RAM side row is accessed. As more RAM side rows are accessed, the hit bitline drops lower in voltage. The hit bitline drives an inverter with a threshold set such that any voltage equal to or lower than the threshold indicates a multi-hit situation. Any voltage higher than the threshold indicates a single hit or “no-hit” situation. Thus, from the voltage of the hit bitline, the presence of a multi-hit condition may be detected.
摘要:
A mechanism is provided for transparent multi-hit correction in associative memories. A content associative memory (CAM) device is provided that transparently and independently executes a precise corrective action in the case of a multiple hit being detected. The wordlines of a CAM array are modified to include a valid bit storage circuit element that indicates whether or not the corresponding wordline is valid or not. In operation, if multiple hits are detected, the multiple hit is signaled to the host system and the particular entries in the CAM array corresponding to the multiple hits are invalidated by setting their associated valid bit storage circuit elements to an invalid value or clearing the value in the associated valid bit storage circuit element. Any data returned to the host system as a result of the multiple hits is invalidated in the host system in response to the signaling of the multiple hits.
摘要:
An apparatus and method for multiple hit (multi-hit) detection in associative memories, such as a content addressable memory (CAM), are provided. The illustrative embodiments include a hit bitline that discharges as RAM side entries of the associative memory are accessed. The hit bitline is precharged high and pulled low by a series of devices that are activated as each RAM side row is accessed. As more RAM side rows are accessed, the hit bitline drops lower in voltage. The hit bitline drives an inverter with a threshold set such that any voltage equal to or lower than the threshold indicates a multi-hit situation. Any voltage higher than the threshold indicates a single hit or “no-hit” situation. Thus, from the voltage of the hit bitline, the presence of a multi-hit condition may be detected.
摘要:
A mechanism is provided for enabling a proper write through during a write-through operation. Responsive to determining the memory access as a write-through operation, first circuitry determines whether a data input signal is in a first state or a second state. Responsive to the data input signal being in the second state, the first circuitry outputs a global write line signal in the first state. Responsive to the global write line signal being in the first state, second circuitry outputs a column select signal in the second state. Responsive to the column select signal being in the second state, third circuitry keeps a downstream read path of the cache access memory at the first state such that data output by the cache memory array is in the first state.