Cache array power savings through a design structure for valid bit detection
    1.
    发明授权
    Cache array power savings through a design structure for valid bit detection 失效
    通过用于有效位检测的设计结构来缓存阵列功耗

    公开(公告)号:US08014215B2

    公开(公告)日:2011-09-06

    申请号:US12635234

    申请日:2009-12-10

    IPC分类号: G11C7/00

    摘要: A mechanism is provided for gating a read access of any row in a cache access memory that has been invalidated. An address decoder in the cache access memory sends a memory access to a non-gated wordline driver and a gated wordline driver associated with the memory access. The non-gated wordline driver outputs the data stored in a valid bit memory cell to the gated wordline driver in response to the non-gated wordline driver determining the memory access as a read access. The gated wordline driver determines whether the data from the valid bit memory cell from the non-gated wordline driver indicates either valid data or invalid data in response to the gated wordline driver determining the memory access as a read access and denies an output of the data in a row of memory cells associated with the gated wordline driver in response to the data being invalid.

    摘要翻译: 提供了一种机制,用于选通已被无效的高速缓存访​​问存储器中的任何行的读取访问。 高速缓存存取存储器中的地址解码器发送存储器访问到非门控字线驱动器和与存储器访问相关联的选通字线驱动器。 响应于非门控字线驱动器将存储器访问确定为读取访问,非门控字线驱动器将存储在有效位存储器单元中的数据输出到门控字线驱动器。 门控字线驱动器确定来自非门控字线驱动器的来自有效位存储器单元的数据是否响应于门控字线驱动器确定存储器访问作为读取访问而指示有效数据或无效数据,并且拒绝数据的输出 在与该门控字幕驱动器相关联的一行存储器单元响应于该数据无效。

    Apparatus for SRAM array power reduction through majority evaluation
    2.
    发明授权
    Apparatus for SRAM array power reduction through majority evaluation 失效
    用于SRAM阵列功率降低的装置通过多数评估

    公开(公告)号:US07468929B2

    公开(公告)日:2008-12-23

    申请号:US11609382

    申请日:2006-12-12

    IPC分类号: G11C5/14

    摘要: A mechanism for reducing the amount of power or energy consumed by an SRAM array when the SRAM array is being accessed is provided. Logic is provided that identifies a polarity of a row of memory cells whose data values are to be read. The polarity of the row of memory cells indicates whether a majority of the data values stored in the row of memory cells are logic 1 data values or logic 0 data values. Based on the polarity, selection logic either selects true data values or complement data values of the memory cells. Additional logic is provided in each memory cell for outputting a true data value to a read bit line and outputting a compliment data value to the read bit line based on the polarity.

    摘要翻译: 提供了当SRAM阵列被访问时减少SRAM阵列消耗的功率或能量的机构。 提供逻辑,其标识要读取其数据值的一行存储器单元的极性。 存储单元行的极性指示存储在存储单元行中的大部分数据值是逻辑1数据值还是逻辑0数据值。 基于极性,选择逻辑选择真实数据值或存储单元的补码数据值。 在每个存储器单元中提供附加的逻辑,用于将真实数据值输出到读位线,并且基于极性将补码数据值输出到读位线。

    APPARATUS AND METHOD FOR SRAM ARRAY POWER REDUCTION THROUGH MAJORITY EVALUATION
    3.
    发明申请
    APPARATUS AND METHOD FOR SRAM ARRAY POWER REDUCTION THROUGH MAJORITY EVALUATION 失效
    通过重大评估进行SRAM阵列功率降低的装置和方法

    公开(公告)号:US20080137450A1

    公开(公告)日:2008-06-12

    申请号:US11609382

    申请日:2006-12-12

    IPC分类号: G11C7/00

    摘要: A mechanism for reducing the amount of power or energy consumed by an SRAM array when the SRAM array is being accessed are provided. Logic is provided for determining the polarity of an incoming row being written to the SRAM cell array. Logic is further provided for storing a polarity value into an additional SRAM cell per row of the SRAM cell array. Logic is also provided for reading an inverted value of the SRAM cells of a row in the SRAM cell array if the row contains more 0's than 1's, as determined based on the polarity value stored in the additional SRAM cell per row. Logic is further provided for signaling to downstream logic whether the data read from the SRAM cells in the row represents the true data values or their complement, as determined based on the polarity value stored in the additional SRAM cell per row.

    摘要翻译: 提供了当SRAM阵列被访问时减少SRAM阵列消耗的功率或能量的机构。 逻辑被提供用于确定被写入SRAM单元阵列的输入行的极性。 进一步提供逻辑用于将极性值存储到每个SRAM单元阵列的附加SRAM单元中。 如果根据存储在每行的附加SRAM单元中的极性值确定的行,如果该行包含多于0的逻辑,则还提供用于读取SRAM单元阵列中的行的SRAM单元的反相值的逻辑。 进一步提供逻辑用于向下游逻辑发信号,从行中的SRAM单元读取的数据是否基于存储在每行的附加SRAM单元中的极性值确定的真实数据值或其补码。

    Preventing Fast Read Before Write in Static Random Access Memory Arrays
    4.
    发明申请
    Preventing Fast Read Before Write in Static Random Access Memory Arrays 失效
    在写入静态随机存取存储器阵列之前防止快速读取

    公开(公告)号:US20110258395A1

    公开(公告)日:2011-10-20

    申请号:US12761618

    申请日:2010-04-16

    摘要: A mechanism is provided for enabling a proper write through during a write-through operation. Responsive to determining the memory access as a write-through operation, first circuitry determines whether a data input signal is in a first state or a second state. Responsive to the data input signal being in the second state, the first circuitry outputs a global write line signal in the first state. Responsive to the global write line signal being in the first state, second circuitry outputs a column select signal in the second state. Responsive to the column select signal being in the second state, third circuitry keeps a downstream read path of the cache access memory at the first state such that data output by the cache memory array is in the first state.

    摘要翻译: 提供了一种机制,用于在直写操作期间实现适当的写入。 响应于将存储器访问确定为直写操作,第一电路确定数据输入信号是处于第一状态还是第二状态。 响应于处于第二状态的数据输入信号,第一电路在第一状态下输出全局写入线信号。 响应于全局写入线信号处于第一状态,第二电路输出处于第二状态的列选择信号。 响应于列选择信号处于第二状态,第三电路将高速缓存存取存储器的下游读取路径保持在第一状态,使得由高速缓冲存储器阵列输出的数据处于第一状态。

    APPARATUS AND METHOD FOR TRANSPARENT MULTI-HIT CORRECTION IN ASSOCIATIVE MEMORIES
    5.
    发明申请
    APPARATUS AND METHOD FOR TRANSPARENT MULTI-HIT CORRECTION IN ASSOCIATIVE MEMORIES 有权
    相关记忆中透明多重校正的装置和方法

    公开(公告)号:US20080140924A1

    公开(公告)日:2008-06-12

    申请号:US11609416

    申请日:2006-12-12

    IPC分类号: G06F12/00

    CPC分类号: G11C15/04 G06F12/1027

    摘要: An apparatus and method for transparent multi-hit correction in associative memories are provided. In one illustrative embodiment, a content associative memory (CAM) device is provided that transparently and independently executes a precise corrective action in the case of a multiple hit being detected. The wordlines of a CAM array are modified to include a valid bit storage circuit element that indicates whether or not the corresponding wordline is valid or not. In operation, if multiple hits are detected, the multiple hit is signaled to the host system and the particular entries in the CAM array corresponding to the multiple hits are invalidated by setting their associated valid bit storage circuit elements to an invalid value or clearing the value in the associated valid bit storage circuit element. Any data returned to the host system as a result of the multiple hits is invalidated in the host system in response to the signaling of the multiple hits.

    摘要翻译: 提供了一种用于关联存储器中的透明多点校正的装置和方法。 在一个说明性实施例中,提供内容关联存储器(CAM)装置,其在检测到多次命中的情况下透明地且独立地执行精确的校正动作。 CAM阵列的字线被修改为包括有效位存储电路元件,其指示对应的字线是否有效。 在操作中,如果检测到多个命中,则将多次命中信号发送到主机系统,并且通过将其相关联的有效位存储电路元件设置为无效值或清除该值来使与多次命中相对应的CAM阵列中的特定条目无效 在相关联的有效位存储电路元件中。 作为多次命中的结果返回到主机系统的任何数据在主机系统中响应于多次命中的信令而无效。

    Cache Array Power Savings Through a Design Structure for Valid Bit Detection
    6.
    发明申请
    Cache Array Power Savings Through a Design Structure for Valid Bit Detection 失效
    缓存阵列通过有效位检测的设计结构节能

    公开(公告)号:US20110141826A1

    公开(公告)日:2011-06-16

    申请号:US12635234

    申请日:2009-12-10

    摘要: A mechanism is provided for gating a read access of any row in a cache access memory that has been invalidated. An address decoder in the cache access memory sends a memory access to a non-gated wordline driver and a gated wordline driver associated with the memory access. The non-gated wordline driver outputs the data stored in a valid bit memory cell to the gated wordline driver in response to the non-gated wordline driver determining the memory access as a read access. The gated wordline driver determines whether the data from the valid bit memory cell from the non-gated wordline driver indicates either valid data or invalid data in response to the gated wordline driver determining the memory access as a read access and denies an output of the data in a row of memory cells associated with the gated wordline driver in response to the data being invalid.

    摘要翻译: 提供了一种机制,用于选通已被无效的高速缓存访​​问存储器中的任何行的读取访问。 高速缓存存取存储器中的地址解码器发送存储器访问到非门控字线驱动器和与存储器访问相关联的选通字线驱动器。 响应于非门控字线驱动器将存储器访问确定为读取访问,非门控字线驱动器将存储在有效位存储器单元中的数据输出到门控字线驱动器。 门控字线驱动器确定来自非门控字线驱动器的来自有效位存储器单元的数据是否响应于门控字线驱动器确定存储器访问作为读取访问而指示有效数据或无效数据,并且拒绝数据的输出 在与该门控字幕驱动器相关联的一行存储器单元响应于该数据无效。

    Multi-hit detection in associative memories
    7.
    发明授权
    Multi-hit detection in associative memories 有权
    联想记忆中的多重检测

    公开(公告)号:US07788444B2

    公开(公告)日:2010-08-31

    申请号:US11609464

    申请日:2006-12-12

    IPC分类号: G06F13/00 G06F13/28 G11C15/00

    CPC分类号: G11C15/04 G06F12/1027

    摘要: Mechanisms for multiple hit (multi-hit) detection in associative memories, such as a content addressable memory (CAM), are provided. The illustrative embodiments include a hit bitline that discharges as RAM side entries of the associative memory are accessed. The hit bitline is precharged high and pulled low by a series of devices that are activated as each RAM side row is accessed. As more RAM side rows are accessed, the hit bitline drops lower in voltage. The hit bitline drives an inverter with a threshold set such that any voltage equal to or lower than the threshold indicates a multi-hit situation. Any voltage higher than the threshold indicates a single hit or “no-hit” situation. Thus, from the voltage of the hit bitline, the presence of a multi-hit condition may be detected.

    摘要翻译: 提供了诸如内容可寻址存储器(CAM)之类的关联存储器中多次命中(多重命中)检测的机制。 示例性实施例包括作为关联存储器的RAM侧条目进行放电的命中位线。 命中位线被预充电高,并被一系列在每个RAM侧行被访问时激活的设备拉低。 随着访问更多的RAM侧行,命中位线的电压降低。 命中位线驱动具有阈值设置的逆变器,使得等于或低于阈值的任何电压指示多重命中情况。 任何高于阈值的电压都表示单次击中或“无命中”情况。 因此,从命中位线的电压可以检测到存在多命中条件。

    Transparent multi-hit correction in associative memories
    8.
    发明授权
    Transparent multi-hit correction in associative memories 有权
    联想记忆中的透明多点校正

    公开(公告)号:US07788443B2

    公开(公告)日:2010-08-31

    申请号:US11609416

    申请日:2006-12-12

    CPC分类号: G11C15/04 G06F12/1027

    摘要: A mechanism is provided for transparent multi-hit correction in associative memories. A content associative memory (CAM) device is provided that transparently and independently executes a precise corrective action in the case of a multiple hit being detected. The wordlines of a CAM array are modified to include a valid bit storage circuit element that indicates whether or not the corresponding wordline is valid or not. In operation, if multiple hits are detected, the multiple hit is signaled to the host system and the particular entries in the CAM array corresponding to the multiple hits are invalidated by setting their associated valid bit storage circuit elements to an invalid value or clearing the value in the associated valid bit storage circuit element. Any data returned to the host system as a result of the multiple hits is invalidated in the host system in response to the signaling of the multiple hits.

    摘要翻译: 提供了一种用于联想记忆中的透明多点校正的机制。 提供内容关联存储器(CAM)装置,其在检测到多重命中的情况下透明地且独立地执行精确的校正动作。 CAM阵列的字线被修改为包括有效位存储电路元件,其指示对应的字线是否有效。 在操作中,如果检测到多个命中,则将多次命中信号发送到主机系统,并且通过将其相关联的有效位存储电路元件设置为无效值或清除该值来使与多次命中相对应的CAM阵列中的特定条目无效 在相关联的有效位存储电路元件中。 作为多次命中的结果返回到主机系统的任何数据在主机系统中响应于多次命中的信令而无效。

    APPARATUS AND METHOD FOR MULTI-HIT DETECTION IN ASSOCIATIVE MEMORIES
    9.
    发明申请
    APPARATUS AND METHOD FOR MULTI-HIT DETECTION IN ASSOCIATIVE MEMORIES 有权
    相关记忆中多重检测的装置和方法

    公开(公告)号:US20080140925A1

    公开(公告)日:2008-06-12

    申请号:US11609464

    申请日:2006-12-12

    IPC分类号: G06F12/00

    CPC分类号: G11C15/04 G06F12/1027

    摘要: An apparatus and method for multiple hit (multi-hit) detection in associative memories, such as a content addressable memory (CAM), are provided. The illustrative embodiments include a hit bitline that discharges as RAM side entries of the associative memory are accessed. The hit bitline is precharged high and pulled low by a series of devices that are activated as each RAM side row is accessed. As more RAM side rows are accessed, the hit bitline drops lower in voltage. The hit bitline drives an inverter with a threshold set such that any voltage equal to or lower than the threshold indicates a multi-hit situation. Any voltage higher than the threshold indicates a single hit or “no-hit” situation. Thus, from the voltage of the hit bitline, the presence of a multi-hit condition may be detected.

    摘要翻译: 提供了诸如内容可寻址存储器(CAM)等关联存储器中的多命中(多次命中)检测的装置和方法。 示例性实施例包括作为关联存储器的RAM侧条目进行放电的命中位线。 命中位线被预充电高,并被一系列在每个RAM侧行被访问时激活的设备拉低。 随着访问更多的RAM侧行,命中位线的电压降低。 命中位线驱动具有阈值设置的逆变器,使得等于或低于阈值的任何电压指示多重命中情况。 任何高于阈值的电压都表示单次击中或“无命中”情况。 因此,从命中位线的电压可以检测到存在多命中条件。

    Preventing fast read before write in static random access memory arrays
    10.
    发明授权
    Preventing fast read before write in static random access memory arrays 失效
    在写入静态随机存取存储器阵列之前防止快速读取

    公开(公告)号:US08375172B2

    公开(公告)日:2013-02-12

    申请号:US12761618

    申请日:2010-04-16

    摘要: A mechanism is provided for enabling a proper write through during a write-through operation. Responsive to determining the memory access as a write-through operation, first circuitry determines whether a data input signal is in a first state or a second state. Responsive to the data input signal being in the second state, the first circuitry outputs a global write line signal in the first state. Responsive to the global write line signal being in the first state, second circuitry outputs a column select signal in the second state. Responsive to the column select signal being in the second state, third circuitry keeps a downstream read path of the cache access memory at the first state such that data output by the cache memory array is in the first state.

    摘要翻译: 提供了一种机制,用于在直写操作期间实现适当的写入。 响应于将存储器访问确定为直写操作,第一电路确定数据输入信号是处于第一状态还是第二状态。 响应于处于第二状态的数据输入信号,第一电路在第一状态下输出全局写入线信号。 响应于全局写入线信号处于第一状态,第二电路输出处于第二状态的列选择信号。 响应于列选择信号处于第二状态,第三电路将高速缓存存取存储器的下游读取路径保持在第一状态,使得由高速缓冲存储器阵列输出的数据处于第一状态。