公开(公告)号：US07962543B2

公开(公告)日：2011-06-14

申请号：US11756885

申请日：2007-06-01

申请人： Michael J. Schulte ,  Carl E. Lemonds, Jr. ,  Dimitri Tan

发明人： Michael J. Schulte ,  Carl E. Lemonds, Jr. ,  Dimitri Tan

IPC分类号： G06F7/535

CPC分类号： G06F7/4873 ,  G06F2207/5356

摘要： A division method includes determining a precision indicator for the division operation that indicates whether the quotient should be a single precision, double precision, or extended precision floating-point number. The division is performed at a rectangular multiplier using the Goldschmidt or Newton-Raphson algorithm. Each algorithm calculates one or more intermediate values in order to determine the quotient. For example, the Goldschmidt algorithm calculates a complement of a product of the dividend and an estimate of the reciprocal of the divisor. The quotient is determined based on a portion of one or more of these intermediate values. Because only a portion of the intermediate value is used, the division can be performed efficiently at the rectangular multiplier, and therefore the quotient can be determined more quickly and still achieve the desired level of precision.

摘要翻译： 分割方法包括确定用于指示商是否应当是单精度，双精度或扩展精度浮点数的除法运算的精度指示符。 使用Goldschmidt或Newton-Raphson算法在矩形乘法器上执行除法。 每个算法计算一个或多个中间值以确定商。 例如，Goldschmidt算法计算股息的乘积的互补和除数的倒数的估计。 基于这些中间值中的一个或多个的一部分来确定商。 因为仅使用中间值的一部分，所以可以在矩形乘法器上有效地执行除法，因此可以更快速地确定商并且仍然达到期望的精度水平。

公开(公告)号：US06256724B1

公开(公告)日：2001-07-03

申请号：US09244674

申请日：1999-02-04

申请人： Dale E. Hocevar ,  Alan Gatherer ,  Carl E. Lemonds, Jr. ,  Ching-Yu Hung

发明人： Dale E. Hocevar ,  Alan Gatherer ,  Carl E. Lemonds, Jr. ,  Ching-Yu Hung

IPC分类号： G06F1316

CPC分类号： G06F9/3879 ,  G06F9/3897

摘要： A data processing system includes a digital signal processor core and a co-processor. The co-processor has a local memory within the address space of the said digital signal processor core. The co-processor responds commands from the digital signal processor core. A direct memory access circuit autonomously transfers data to and from the local memory of the co-processor. Co-processor commands are stored in a command FIFO memory mapped to a predetermined memory address. Control commands includes a receive data synchronism command stalling the co-processor until completion of a memory transfer into the local memory. A send data synchronism command causes the co-processor to signal the direct memory access circuit to trigger memory transfer out of the local memory. An interrupt command causes the co-processor to interrupt the digital signal processor core.

摘要翻译： 数据处理系统包括数字信号处理器核和协处理器。 协处理器在所述数字信号处理器核心的地址空间内具有本地存储器。 协处理器响应来自数字信号处理器核心的命令。 直接存储器访问电路自主地将数据传送到协处理器的本地存储器和/或从协处理器的本地存储器传送数据。 协处理器命令存储在映射到预定存储器地址的命令FIFO存储器中。 控制命令包括停止协处理器的接收数据同步命令，直到完成到本地存储器的存储器传送。 发送数据同步命令使协处理器向直接存储器访问电路发出信号，以触发从本地存储器传出的存储器。 中断命令使协处理器中断数字信号处理器内核。

公开(公告)号：US06298366B1

公开(公告)日：2001-10-02

申请号：US09244973

申请日：1999-02-04

申请人： Alan Gatherer ,  Carl E. Lemonds, Jr. ,  Dale E. Hocevar ,  Ching-Yu Hung

发明人： Alan Gatherer ,  Carl E. Lemonds, Jr. ,  Dale E. Hocevar ,  Ching-Yu Hung

IPC分类号： G06F748

CPC分类号： G06F7/5443

摘要： A reconfigurable co-processor adapted for multiple multiply-accumulate operations includes plural pairs of multipliers, plural first adders receiving respective product outputs from a pairs of multipliers, and at least one second adder receiving sum outputs from a corresponding pair of first adders. The co-processor includes sign extend circuits at the output of each multiplier. One multiplier of each pair has a fixed left shift circuit that left shifts the product output a predetermined number of bits. The other multiplier in each pair includes a right shift circuit that right shifts the product output the number of bits. Multiplexers at the output of the first multiplier in each pair select the sign extended or the left shifted products. Multiplexers at the output of the second multiplier in each pair select the product, the right shifted product or pass through the inputs. The sign extend circuit for the second multiplier follows the multiplexer. Third adders receive the sum outputs of the second adders and produce a third sum output. These third adders include plural selectable output accumulators and variable right shifter at their outputs. The third adders may separately sum the product sums from four multipliers each. Alternatively, the third adders may accumulate the products of eight multipliers.

摘要翻译： 适用于多重乘法运算的可重配置协处理器包括多对乘法器，多个第一加法器，从一对乘法器接收相应的乘积输出，以及至少一个第二加法器，从相应的第一加法器对接收和输出。 协处理器在每个乘法器的输出端包括符号扩展电路。 每对的一个乘法器具有固定的左移位电路，其使乘积输出偏移预定数量的位。 每对中的另一个乘法器包括一个右移位电路，用于将乘积输出向右移位位数。 每对中第一乘法器输出端的多路复用器选择扩展符号或左移符号。 每对中第二乘法器输出端的多路复用器选择产品，右移产品或通过输入。 第二乘法器的符号扩展电路跟随多路复用器。 第三加法器接收第二加法器的和输出并产生第三和输出。 这些第三加法器在其输出端包括多个可选输出累加器和可变右移位器。 第三加法器可以分别将乘积和乘以四个乘法器。 或者，第三加法器可以累积八个乘法器的乘积。