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1.发明授权公开(公告)号：US06256724B1
公开(公告)日：2001-07-03
申请号：US09244674
申请日：1999-02-04
IPC分类号： G06F1316
CPC分类号： G06F9/3879 , G06F9/3897
摘要： A data processing system includes a digital signal processor core and a co-processor. The co-processor has a local memory within the address space of the said digital signal processor core. The co-processor responds commands from the digital signal processor core. A direct memory access circuit autonomously transfers data to and from the local memory of the co-processor. Co-processor commands are stored in a command FIFO memory mapped to a predetermined memory address. Control commands includes a receive data synchronism command stalling the co-processor until completion of a memory transfer into the local memory. A send data synchronism command causes the co-processor to signal the direct memory access circuit to trigger memory transfer out of the local memory. An interrupt command causes the co-processor to interrupt the digital signal processor core.
摘要翻译： 数据处理系统包括数字信号处理器核和协处理器。 协处理器在所述数字信号处理器核心的地址空间内具有本地存储器。 协处理器响应来自数字信号处理器核心的命令。 直接存储器访问电路自主地将数据传送到协处理器的本地存储器和/或从协处理器的本地存储器传送数据。 协处理器命令存储在映射到预定存储器地址的命令FIFO存储器中。 控制命令包括停止协处理器的接收数据同步命令，直到完成到本地存储器的存储器传送。 发送数据同步命令使协处理器向直接存储器访问电路发出信号，以触发从本地存储器传出的存储器。 中断命令使协处理器中断数字信号处理器内核。
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公开(公告)号：US06298366B1
公开(公告)日：2001-10-02
申请号：US09244973
申请日：1999-02-04
IPC分类号： G06F748
CPC分类号： G06F7/5443
摘要： A reconfigurable co-processor adapted for multiple multiply-accumulate operations includes plural pairs of multipliers, plural first adders receiving respective product outputs from a pairs of multipliers, and at least one second adder receiving sum outputs from a corresponding pair of first adders. The co-processor includes sign extend circuits at the output of each multiplier. One multiplier of each pair has a fixed left shift circuit that left shifts the product output a predetermined number of bits. The other multiplier in each pair includes a right shift circuit that right shifts the product output the number of bits. Multiplexers at the output of the first multiplier in each pair select the sign extended or the left shifted products. Multiplexers at the output of the second multiplier in each pair select the product, the right shifted product or pass through the inputs. The sign extend circuit for the second multiplier follows the multiplexer. Third adders receive the sum outputs of the second adders and produce a third sum output. These third adders include plural selectable output accumulators and variable right shifter at their outputs. The third adders may separately sum the product sums from four multipliers each. Alternatively, the third adders may accumulate the products of eight multipliers.
摘要翻译： 适用于多重乘法运算的可重配置协处理器包括多对乘法器，多个第一加法器，从一对乘法器接收相应的乘积输出，以及至少一个第二加法器，从相应的第一加法器对接收和输出。 协处理器在每个乘法器的输出端包括符号扩展电路。 每对的一个乘法器具有固定的左移位电路，其使乘积输出偏移预定数量的位。 每对中的另一个乘法器包括一个右移位电路，用于将乘积输出向右移位位数。 每对中第一乘法器输出端的多路复用器选择扩展符号或左移符号。 每对中第二乘法器输出端的多路复用器选择产品，右移产品或通过输入。 第二乘法器的符号扩展电路跟随多路复用器。 第三加法器接收第二加法器的和输出并产生第三和输出。 这些第三加法器在其输出端包括多个可选输出累加器和可变右移位器。 第三加法器可以分别将乘积和乘以四个乘法器。 或者，第三加法器可以累积八个乘法器的乘积。
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公开(公告)号：US06690750B1
公开(公告)日：2004-02-10
申请号：US09471430
申请日：1999-12-23
申请人： Dale E. Hocevar , Alan Gatherer
发明人： Dale E. Hocevar , Alan Gatherer
IPC分类号： H03D100
CPC分类号： H03M13/6502 , H03M13/4107 , H03M13/4169 , H03M13/6569
摘要： A Viterbi decoder system is provided in accordance with the present invention. The decoder system includes a State Metric Update unit including a state metric memory and a cascaded Add/Compare/Select (ACS) unit. The cascaded ACS unit comprises a plurality of serially coupled ACS stages for performing a plurality of ACS operations in conjunction with the state metric memory. An ACS stage is operable to identify a plurality of path decisions and communicate the identified path decisions to a next ACS stage coupled thereto. A Traceback unit is provided for storing a set of accumulated path decisions in a traceback memory associated therewith, and performing a traceback on the set of accumulated path decisions. The path decisions associated with the ACS stage and the next ACS stage are accumulated as a set during the ACS operations before being written to the traceback memory, thereby minimizing accesses to the traceback memory.
摘要翻译： 根据本发明提供维特比解码器系统。 解码器系统包括状态度量更新单元，其包括状态度量存储器和级联的加法/比较/选择（ACS）单元。 级联的ACS单元包括多个串联耦合的ACS级，用于结合状态度量存储器执行多个ACS操作。 ACS阶段可操作以识别多个路径决策，并将所识别的路径决定传递到与其耦合的下一个ACS阶段。 提供追溯单元用于在与之相关联的回溯存储器中存储一组累积的路径决策，并且对该组累积的路径决定执行回溯。 与ACS阶段和下一个ACS阶段相关联的路径决策在被写入回溯存储器之前在ACS操作期间作为集合被累积，从而最小化对回溯存储器的访问。
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4.发明授权公开(公告)号：US07669109B2
公开(公告)日：2010-02-23
申请号：US11463236
申请日：2006-08-08
申请人： Dale E. Hocevar
发明人： Dale E. Hocevar
CPC分类号： H04L1/0052 , H03M13/1114 , H03M13/1137 , H03M13/1148 , H03M13/116 , H03M13/118 , H03M13/1185 , H04L1/005 , H04L1/0057
摘要： A low density parity check (LDPC) code for a belief propagation decoder circuit is disclosed. LDPC code is arranged as a macro matrix (H) representing block columns and block rows of a corresponding parity check matrix (Hpc). Each non-zero entry corresponds to a permutation matrix with a shift corresponding to the position of the permutation matrix entry in the macro matrix. The block columns are grouped, so that only one column in the group contributes to the parity check sum in a row. A parity check value estimate memory is arranged in banks logically connected in various data widths and depths. A parallel adder generates extrinsic estimates for generating new parity check value estimates that are forwarded to bit update circuits for updating of probability values. Parallelism, time-sequencing of ultrawide parity check rows, and pairing of circuitry to handle ultrawide code rows, are also disclosed.
摘要翻译： 公开了一种用于置信传播解码器电路的低密度奇偶校验（LDPC）码。 LDPC码被布置为表示相应奇偶校验矩阵（Hpc）的块列和块行的宏矩阵（H）。 每个非零条目对应于具有对应于宏矩阵中的置换矩阵条目的位置的移位的置换矩阵。 块列被分组，使得组中只有一列有助于一行中的奇偶校验和。 奇偶校验值估计存储器被布置在以各种数据宽度和深度逻辑连接的存储体中。 并行加法器产生用于生成新的奇偶校验值估计的外在估计，其被转发到位更新电路以更新概率值。 还公开了平行度，超宽奇偶校验行的时间序列以及用于处理超级代码行的电路的配对。
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公开(公告)号：US20090049363A1
公开(公告)日：2009-02-19
申请号：US12258575
申请日：2008-10-27
申请人： Dale E. Hocevar
发明人： Dale E. Hocevar
CPC分类号： H03M13/1185 , H03M13/118 , H03M13/255
摘要： Encoder circuitry for applying a low-density parity check (LDPC) code to information words is disclosed. The encoder circuitry takes advantage of a macro matrix arrangement of the LDPC parity check matrix in which the parity portion of the parity check matrix is arranged as a macro matrix in which all block columns but one define a recursion path. The parity check matrix is factored so that the last block column of the parity portion includes an invertible cyclic matrix as its entry in a selected block row, with all other parity portion columns in that selected block row being zero-valued, thus permitting solution of the parity bits for that block column from the information portion of the parity check matrix and the information word to be encoded. Solution of the other parity bits can then be readily performed, from the original (non-factored) parity portion of the parity check matrix, following the recursion path.
摘要翻译： 公开了一种用于将低密度奇偶校验（LDPC）码应用于信息字的编码器电路。 编码器电路利用LDPC奇偶校验矩阵的宏矩阵布置，其中奇偶校验矩阵的奇偶校验部分被布置为宏矩阵，其中所有块列都定义了递归路径。 奇偶校验矩阵被考虑，使得奇偶校验部分的最后一个块列包括可选循环矩阵作为其在所选块行中的条目，其中所选择的块行中的所有其他奇偶校验部分列为零值，从而允许 来自奇偶校验矩阵的信息部分的该块列的奇偶校验位和要编码的信息字。 然后可以从递归路径之后的奇偶校验矩阵的原始（非因子的）奇偶校验部分容易地执行其他奇偶校验位的解。
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6.发明申请公开(公告)号：US20110055655A1
公开(公告)日：2011-03-03
申请号：US12512506
申请日：2009-09-22
申请人： Dale E. Hocevar
发明人： Dale E. Hocevar
CPC分类号： H04L1/0052 , H03M13/1114 , H03M13/1137 , H03M13/1148 , H03M13/116 , H03M13/118 , H03M13/1185 , H04L1/005 , H04L1/0057
摘要： A network element receiving signals from the network over a communications channel via transceiver circuitry. The network element has a host interface for communicating to a host system, decoded signals corresponding signals received from the network. Demodulator circuitry demodulates the signals into a data stream. Circuitry for decoding the data stream according to a sequence of operations is provided. The sequence of operations includes receiving a set of input values corresponding to input nodes of the macro parity check matrix. Estimating a check node value using values of other input nodes contributing to the parity check sum. Evaluating a probability value using the estimates of the check node values for that input node. The The operations are repeated until termination point is reached.
摘要翻译： 网络元件经由收发器电路通过通信信道从网络接收信号。 网络元件具有用于与主机系统通信的主机接口，对从网络接收的相应信号进行解码的信号。 解调器电路将信号解调为数据流。 提供了根据操作顺序解码数据流的电路。 操作序列包括接收与宏奇偶校验矩阵的输入节点对应的一组输入值。 使用有助于奇偶校验和的其他输入节点的值来估计校验节点值。 使用该输入节点的校验节点值的估计来评估概率值。 重复操作，直到达到终止点。
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公开(公告)号：US20070283215A1
公开(公告)日：2007-12-06
申请号：US11744357
申请日：2007-05-04
申请人： Yuming Zhu , Yanni Chen , Dale E. Hocevar , Manish Goel
发明人： Yuming Zhu , Yanni Chen , Dale E. Hocevar , Manish Goel
IPC分类号： H03M13/00
CPC分类号： H03M13/1111
摘要： A method and systems for reducing the complexity of a parity checker are described herein. In at least some preferred embodiments, a parity-check decoder includes column store units and one or more alignment units, which are coupled to the column store units. The column store units outnumber the alignments units.
摘要翻译： 本文描述了用于降低奇偶校验器的复杂度的方法和系统。 在至少一些优选实施例中，奇偶校验解码器包括列存储单元和耦合到列存储单元的一个或多个对准单元。 列存储单位超出排列单位。
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公开(公告)号：US06934343B2
公开(公告)日：2005-08-23
申请号：US10007977
申请日：2001-11-13
申请人： Dale E. Hocevar
发明人： Dale E. Hocevar
CPC分类号： H03M13/4169 , H03M13/3961 , H03M13/41 , H03M13/4107 , H03M13/6583 , H03M13/6586
摘要： By utilizing an additional counter and monitoring the maximum state metric at each stage, only forward progressing modulo wrap-arounds will occur and these can be counted. After decoding this count information, it can be used with the initial and final state metric values from the decoder to compute the desired full path metric. The method only requires monitoring state metric wrap-arounds moving in one direction and hence only needs to increment the extra counter as opposed to having to do likewise in the opposite direction. In another embodiment, the method can handle both forward and backward progressions by incrementing and decrementing a counter.
摘要翻译： 通过利用附加计数器并监视每个阶段的最大状态度量，只会发生向前进行的模数回绕，并且可以计数这些。 在对该计数信息进行解码之后，可以使用来自解码器的初始和最终状态度量值来计算所需的全路径度量。 该方法仅需要监视在一个方向上移动的状态度量环绕，因此仅需要增加额外的计数器，而不必在相反方向上进行相同操作。 在另一个实施例中，该方法可以通过递增和递减计数器来处理向前和向后的进程。
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公开(公告)号：US06901118B2
公开(公告)日：2005-05-31
申请号：US09739860
申请日：2000-12-18
CPC分类号： H03M13/6502 , H03M13/4107 , H03M13/4169 , H03M13/6505
摘要： A Viterbi decoder system is provided in accordance with the present invention. The decoder system includes a State Metric Update unit including a state metric memory and a cascaded Add/Compare/Select (ACS) unit. The cascaded ACS unit comprises a plurality of serially coupled ACS stages for performing a plurality of ACS operations in conjunction with the state metric memory. An ACS stage is operable to identify a plurality of path decisions and path differences and communicate the identified path decisions and the identified path differences to a next ACS stage coupled thereto. The decoder also includes a Traceback unit for storing a set of accumulated path decisions in a traceback memory associated therewith, and performing a traceback on the set of accumulated path decisions. The path decisions associated with the ACS stage and the next ACS stage are accumulated as a set during the ACS operations before being written to the traceback memory, thereby minimizing accesses to the traceback memory. The path differences associated with the ACS stage and the next ACS stage provide a reliability estimation of the correctness of the path decisions.
摘要翻译： 根据本发明提供维特比解码器系统。 解码器系统包括状态度量更新单元，其包括状态度量存储器和级联的加法/比较/选择（ACS）单元。 级联的ACS单元包括多个串联耦合的ACS级，用于结合状态度量存储器执行多个ACS操作。 ACS阶段可操作以识别多个路径决策和路径差异，并将所识别的路径决定和所识别的路径差传送到与其耦合的下一个ACS阶段。 解码器还包括追溯单元，用于在与其相关联的回溯存储器中存储一组累积的路径决策，并且对该组累积路径决定执行回溯。 与ACS阶段和下一个ACS阶段相关联的路径决策在被写入回溯存储器之前在ACS操作期间作为集合被累积，从而最小化对回溯存储器的访问。 与ACS阶段和下一个ACS阶段相关的路径差异提供了路径决策的正确性的可靠性估计。
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公开(公告)号：US08381079B2
公开(公告)日：2013-02-19
申请号：US12258575
申请日：2008-10-27
申请人： Dale E. Hocevar
发明人： Dale E. Hocevar
IPC分类号： H03M13/00
CPC分类号： H03M13/1185 , H03M13/118 , H03M13/255
摘要： Encoder circuitry for applying a low-density parity check (LDPC) code to information words is disclosed. The encoder circuitry takes advantage of a macro matrix arrangement of the LDPC parity check matrix in which the parity portion of the parity check matrix is arranged as a macro matrix in which all block columns but one define a recursion path. The parity check matrix is factored so that the last block column of the parity portion includes an invertible cyclic matrix as its entry in a selected block row, with all other parity portion columns in that selected block row being zero-valued, thus permitting solution of the parity bits for that block column from the information portion of the parity check matrix and the information word to be encoded. Solution of the other parity bits can then be readily performed, from the original (non-factored) parity portion of the parity check matrix, following the recursion path.
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