公开(公告)号：US06496890B1

公开(公告)日：2002-12-17

申请号：US09454681

申请日：1999-12-03

Applicant: Michael Joseph Azevedo ,  Brent Cameron Beardsley ,  Bitwoded Okbay ,  Carol Spanel ,  Andrew Dale Walls

Inventor： Michael Joseph Azevedo ,  Brent Cameron Beardsley ,  Bitwoded Okbay ,  Carol Spanel ,  Andrew Dale Walls

IPC: G06F1300

CPC classification number: G06F13/4036 ,  G06F13/28

Abstract: A shared bus hang prevention and recovery scheme for a data communication system is provided, where a shared bus is connected to a plurality of bus masters and corresponding slaves and located between an external bus connected to a system processor, and an internal bus connected to an internal processor. Some of the masters are associated with the external bus and others are associated with the internal bus, and one of the bus masters is a control master associated with the internal processor. The scheme utilizes a shared bus hang prevention and recovery device having a circuitry and a control code. The circuitry is timing each pending request of the control master for the shared bus and initiating bus recovery if the shared bus is hung up, when the control master exceeded a pre-determined time period allowed for waiting to acquire the shared bus control and complete the transfer on the shared bus. The control code is used for monitoring and controlling the circuitry and terminating the transfer in progress causing the shared bus hang-up. During the bus recovery the circuitry prevents bus request grants to the master attached to the external bus until the master subsequent reset, and the control program instructions initiates transfers for all pending requests for the shared bus from the control master queue. Each transfer is being timed and terminated if the shared bus is hung up again. Upon the control master queue clearing, the internal processor executes the control program instructions to reset and reinitialize all masters and slaves on the shared bus.

Abstract translation: 提供了一种用于数据通信系统的共享总线挂起预防和恢复方案，其中共享总线连接到多个总线主机和相应的从站，并且位于连接到系统处理器的外部总线与连接到系统处理器的内部总线之间 内部处理器 一些主机与外部总线相关，其他主机与内部总线相关，其中一个总线主机是与内部处理器相关的控制主机。 该方案利用具有电路和控制码的共享总线挂起防止和恢复装置。 如果控制主机超过了允许等待获取共享总线控制的预定时间段并且完成了共享总线控制并且完成 在共享总线上传输。 控制代码用于监视和控制电路，并终止正在进行的传输，从而导致共享总线挂断。 在总线恢复期间，电路阻止对连接到外部总线的主机的总线请求授权，直到主机后续复位，并且控制程序指令从控制主机队列开始对所有未决请求的共享总线的传输。 如果共享总线再次挂起，则每次传输都将被定时和终止。 当控制主队列清除时，内部处理器执行控制程序指令，以复位和重新初始化共享总线上的所有主机和从机。

公开(公告)号：US07073030B2

公开(公告)日：2006-07-04

申请号：US10153966

申请日：2002-05-22

Applicant: Michael Joseph Azevedo ,  Carol Spanel ,  Andrew Dale Walls

Inventor： Michael Joseph Azevedo ,  Carol Spanel ,  Andrew Dale Walls

IPC: G06F12/00

CPC classification number: G06F12/127 ,  G06F12/0862 ,  G06F12/0897 ,  G06F2212/6024

Abstract: A method and apparatus for increasing the processing speed of processors and increasing the data hit ratio is disclosed herein. The method increases the processing speed by providing a non-L1 instruction caching that uses prefetch to increase the hit ratio. Cache lines in a cache set are buffered, wherein the cache lines have a parameter indicating data selection characteristics associated with each buffered cache line. Then which buffered cache lines to cast out and/or invalidate is determined based upon the parameter indicating data selection characteristics.

公开(公告)号：US06519666B1

公开(公告)日：2003-02-11

申请号：US09412990

申请日：1999-10-05

Applicant: Michael Joseph Azevedo ,  Carol Spanel ,  Andrew Dale Walls

Inventor： Michael Joseph Azevedo ,  Carol Spanel ,  Andrew Dale Walls

IPC: G06F13368

CPC classification number: G06F13/362

Abstract: A shared bus arbitration scheme for a data communication system is provided, where a shared bus is connected to a plurality of bus masters and resources, some resources having higher priority than the others and including a peripheral device. Each master may request control of the shared bus and is adapted to perform short transfers and long burst transfers on the shared bus between a resource and the master. A shared bus arbiter is utilized for dynamically determining the highest priority request between a number of shared bus requests, and granting control of the shared bus to the highest priority requesting bus master. The arbiter utilizes a three-level priority hierarchy arbitration scheme where the highest priority level is given to short message transfer requests on the higher-priority system resources, the intermediate priority level is given to short message transfer requests on the lower-priority system resources, if there are no outstanding higher priority level requests, and the lowest priority level is given for long burst transfers, if there are no outstanding short message transfer requests.

Abstract translation: 提供了一种用于数据通信系统的共享总线仲裁方案，其中共享总线连接到多个总线主机和资源，一些资源具有比其他资源更高的优先级，并且包括外围设备。 每个主机可以请求对共享总线的控制，并且适于在资源和主机之间的共享总线上执行短传输和长突发传输。 共享总线仲裁器用于动态地确定多个共享总线请求之间的最高优先级请求，以及授予对最高优先级请求总线主机的共享总线的控制。 仲裁器采用三级优先级分级仲裁方案，其中优先级较高的优先级优先级较高优先级系统资源上的短消息传输请求，中间优先权级别给予低优先级系统资源上的短消息传输请求， 如果没有突出的较高优先级请求，并且对于长突发传输给出最低优先级，则如果没有未完成的短消息传送请求。

公开(公告)号：US08032816B2

公开(公告)日：2011-10-04

申请号：US11757221

申请日：2007-06-01

Applicant: Carol Spanel ,  Andrew Dale Walls

Inventor： Carol Spanel ,  Andrew Dale Walls

IPC: G11C29/00

CPC classification number: G11C29/52 ,  G06F11/1012 ,  G11C5/04 ,  G11C29/44 ,  G11C2029/0409 ,  G11C2029/0411

Abstract: An apparatus and method for distinguishing correctable bit errors in memory. A bit error detection module detects a correctable bit error in a memory in response to a READ operation. The correctable bit error is correctable using error-correcting code. The READ operation is generated during normal operation. A comparison module compares an error location indicator with a stored error location indicator. The error location indicator includes a memory location of the correctable bit error. The stored error location indicator corresponds to a previously stored error location indicator of a previous correctable bit error. A storage module stores the error location indicator if the comparison module determines that the error location indicator differs from a stored error location indicator. An error counter module increases an error counter corresponding to the error location indicator if the comparison module determines that the error location indicator matches a stored error location indicator.

Abstract translation: 用于区分存储器中可校正位错误的装置和方法。 响应于READ操作，位错误检测模块检测存储器中的可校正位错误。 使用纠错码可纠正位错误。 在正常操作期间产生READ操作。 比较模块将错误位置指示器与存储的错误位置指示器进行比较。 错误位置指示符包括可纠正位错误的存储位置。 存储的错误位置指示符对应于先前存储的可纠错位错误的错误位置指示符。 如果比较模块确定错误位置指示符与存储的错误位置指示符不同，则存储模块存储错误位置指示符。 如果比较模块确定错误位置指示符与存储的错误位置指示符匹配，则错误计数器模块增加与错误位置指示符相对应的错误计数器。

公开(公告)号：US07971124B2

公开(公告)日：2011-06-28

申请号：US11757162

申请日：2007-06-01

Applicant: Carol Spanel ,  Andrew Dale Walls

Inventor： Carol Spanel ,  Andrew Dale Walls

IPC: G11C29/00

CPC classification number: G11C29/44 ,  G06F11/1012 ,  G11C5/04 ,  G11C29/52 ,  G11C2029/0409 ,  G11C2029/0411

Abstract: An apparatus, system, and method are disclosed for distinguishing correctable bit errors in memory. A bit error detection module detects a correctable bit error in memory. The correctable bit error is correctable using error-correcting code (“ECC”). A comparison module compares an error location indicator with a stored error location indicator. The error location indicator is a location of the correctable bit error. The stored error location indicator includes to at least one previously stored error location indicator of a previously detected correctable bit error. A storage module stores the error location indicator in response to the comparison module determining that the error location indicator differs from a stored error location indicator. A bit error counter module increases a random bit error counter if the comparison module determines that the error location indicator differs from a stored error location indicator and does not increase the random bit error counter otherwise.

Abstract translation: 公开了用于区分存储器中的可校正位错误的装置，系统和方法。 位错误检测模块检测存储器中可纠正的位错误。 使用纠错码（“ECC”）可纠正位错误。 比较模块将错误位置指示器与存储的错误位置指示器进行比较。 错误位置指示符是可纠正位错误的位置。 存储的错误位置指示符包括至少一个先前存储的先前检测到的可校正位错误的错误位置指示符。 存储模块响应于比较模块确定错误位置指示符与存储的错误位置指示符不同而存储错误位置指示符。 如果比较模块确定错误位置指示符与存储的错误位置指示符不同，则错误计数器模块会增加随机位错误计数器，否则不会增加随机位错误计数器。

公开(公告)号：US07284153B2

公开(公告)日：2007-10-16

申请号：US10715266

申请日：2003-11-17

Applicant: Bitwoded Okbay ,  Carol Spanel ,  Andrew Dale Walls

Inventor： Bitwoded Okbay ,  Carol Spanel ,  Andrew Dale Walls

IPC: G06F11/00

CPC classification number: G06F11/3636 ,  G06F11/364

Abstract: A diagnostic tracing logger is presented for use in a multithread environment in which diagnostic trace log entries are captured and recorded. The trace logs are composed of sequences of memory addresses used to access instructions and operands, instruction op-codes and register specifiers, sequences of memory addresses, branch instructions or exceptions, the contents of registers or semiconductor memory locations, and the like. In one embodiment, a software module configures a plurality of buffers to capture bus traces, each trace triggered by a specific pattern. A buffer controller manages transfer of diagnostic trace information from the plurality of buffers to a diagnostic log without using processor memory cycles. The trace information is transferred to a selected buffer using a processor cache flush instruction. Diagnostic trace logging facilitates diagnosis of complex system and software interactions without the cost and overhead of prior art trace logging techniques.

Abstract translation: 呈现诊断跟踪记录器，用于在其中捕获和记录诊断跟踪日志条目的多线程环境中使用。 跟踪日志由用于访问指令和操作数，指令操作码和寄存器说明符，存储器地址序列，分支指令或异常，寄存器或半导体存储器位置的内容等的存储器地址的序列组成。 在一个实施例中，软件模块配置多个缓冲器以捕获总线迹线，每个跟踪由特定模式触发。 缓冲器控制器管理诊断跟踪信息从多个缓冲器到诊断日志的传送，而不使用处理器存储器周期。 使用处理器高速缓存刷新指令将跟踪信息传输到选定的缓冲区。 诊断跟踪记录便于诊断复杂的系统和软件交互，而不需要现有技术跟踪记录技术的成本和开销。

公开(公告)号：US07627716B2

公开(公告)日：2009-12-01

申请号：US10990039

申请日：2004-11-15

Applicant: Michael Thomas Benhase ,  James Chien-Chiung Chen ,  Yu-Cheng Hsu ,  Matthew Joseph Kalos ,  Carol Spanel ,  Andrew Dale Walls

Inventor： Michael Thomas Benhase ,  James Chien-Chiung Chen ,  Yu-Cheng Hsu ,  Matthew Joseph Kalos ,  Carol Spanel ,  Andrew Dale Walls

IPC: G06F13/00 ,  G06F3/00

CPC classification number: G06F12/0866 ,  G06F12/1081

Abstract: Provided are a method, system, and program for an adaptor to read and write to system memory. A plurality of blocks of data to write to storage are received at an adaptor. The blocks of data are added to a buffer in the adaptor. A determination is made of pages in a memory device and I/O requests are generated to write the blocks in the buffer to the determined pages, wherein two I/O requests are generated to write to one block split between two pages in the memory device. The adaptor executes the generated I/O requests to write the blocks in the buffer to the determined pages in the memory device.

Abstract translation: 提供了适配器读取和写入系统内存的方法，系统和程序。 在适配器处接收要写入存储器的多个数据块。 数据块被添加到适配器中的缓冲区。 确定存储器设备中的页面并且生成I / O请求以将缓冲器中的块写入到所确定的页面，其中生成两个I / O请求以写入存储器设备中的两个页面之间的一个块分割 。 适配器执行生成的I / O请求，将缓冲区中的块写入存储器设备中确定的页面。

公开(公告)号：US20080301345A1

公开(公告)日：2008-12-04

申请号：US11754821

申请日：2007-05-29

Applicant: Stephen L. Blinick ,  Carol Spanel ,  Andrew Dale Walls

Inventor： Stephen L. Blinick ,  Carol Spanel ,  Andrew Dale Walls

IPC: G06F13/00

CPC classification number: G06F13/385

Abstract: One embodiment of an adapter card in accordance with the invention includes a circuit board connectable to a motherboard of a computer system. A logic chip is connected to the circuit board to provide functionality to the adapter card. One or more programmable devices are connected to the circuit board and store data read by the logic chip upon initialization. This data may include first character data to program the logic chip to have a first character and second character data to program the logic chip to have a second character. A switching mechanism is provided to switch between the first and second character data in response to an external input, thereby causing the logic chip to read one of the first and second character data.

Abstract translation: 根据本发明的适配器卡的一个实施例包括可连接到计算机系统的主板的电路板。 逻辑芯片连接到电路板以向适配器卡提供功能。 一个或多个可编程设备连接到电路板，并在初始化时存储由逻辑芯片读取的数据。 该数据可以包括用于对逻辑芯片编程以具有第一字符和第二字符数据的第一字符数据，以将逻辑芯片编程为具有第二字符。 提供切换机制以响应于外部输入在第一和第二字符数据之间切换，从而使逻辑芯片读取第一和第二字符数据之一。

公开(公告)号：US20080065810A1

公开(公告)日：2008-03-13

申请号：US11530393

申请日：2006-09-08

Applicant: Carol Spanel ,  Andrew Dale Walls

Inventor： Carol Spanel ,  Andrew Dale Walls

IPC: G06F12/08 ,  G06F12/00

CPC classification number: G06F11/348 ,  G06F11/3471

Abstract: A system and method for recording trace data while conserving cache resources includes generating trace data and creating a cache line containing the trace data. The cache line is assigned a tag which corresponds to an intermediate address designated for processing the trace data. The cache line also contains embedded therein an actual address in memory for storing the trace data, which may include either a real address or a virtual address. The cache line may be received at the intermediate address and parsed to read the actual address. The trace data may then be written to a location in memory corresponding to the actual address. By routing trace data through a designated intermediate address, CPU cache may be conserved for other more important or more frequently accessed data.

Abstract translation: 用于在保存缓存资源的同时记录跟踪数据的系统和方法包括生成跟踪数据并创建包含跟踪数据的高速缓存行。 为缓存线分配一个标签，该标签对应于指定用于处理跟踪数据的中间地址。 高速缓存线还包括在其中嵌入存储跟踪数据的存储器中的实际地址，其可以包括实际地址或虚拟地址。 高速缓存行可以在中间地址处被接收并被解析以读取实际地址。 然后可以将跟踪数据写入与实际地址相对应的存储器中的位置。 通过路由跟踪数据通过指定的中间地址，CPU缓存可以保存为其他更重要或更频繁访问的数据。

公开(公告)号：US07085859B2

公开(公告)日：2006-08-01

申请号：US10437554

申请日：2003-05-14

Applicant: James Chien-Chiung Chen ,  Carol Spanel ,  Andrew Dale Walls ,  Lih-Chung Kuo

Inventor： James Chien-Chiung Chen ,  Carol Spanel ,  Andrew Dale Walls ,  Lih-Chung Kuo

IPC: G06F3/00 ,  G06F13/00 ,  G06F13/14

CPC classification number: G06F13/385

Abstract: A method, apparatus and program storage device for automatically presenting status from a host bus adapter until an error is detected is provided. Data is transmitted between the host bus adapter and a host. The host performs data transmission validation and determines whether data transmission was successful. The host bus adapter automatically sends status information when data transmission was successful, else the host bus adapter waits for status type identification from the host for transmission of data.

Abstract translation: 提供一种用于自动呈现来自主机总线适配器的状态直到检测到错误的方法，装置和程序存储装置。 数据在主机总线适配器和主机之间传输。 主机执行数据传输验证，并确定数据传输是否成功。 主机总线适配器在数据传输成功时自动发送状态信息，否则主机总线适配器等待来自主机的数据传输的状态类型识别。