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1.发明授权Process for designing base platforms for IC design to permit resource recovery and flexible macro placement, base platform for ICs, and process of creating ICs 有权设计IC设计的基础平台以允许资源恢复和灵活的宏放置，IC的基础平台和创建IC的过程的过程公开(公告)号：US07216323B2
公开(公告)日：2007-05-08
申请号：US10976518
申请日：2004-10-29
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： Base platforms customizable into ICs are designed by identifying a plurality of macros for placement on the platform, each macro being defined in part by a plurality of elements that perform respective functions of the macro. Identical elements in a plurality of macros are identified, and a common element is placed on the platform for an identical element of at least two macros. All other elements of the macros are placed at locations on the platform relative to the common element as to satisfy macro placement rules for each macro. Identical elements can be identified by identifying similar elements in a plurality of macros, and creating a common element generic to the similar elements. The user designs a metalization layer to select macros and configure common elements to the selected macros.
摘要翻译： 通过识别用于放置在平台上的多个宏来设计可定制成IC的基本平台，每个宏部分地由执行宏的相应功能的多个元素定义。 识别多个宏中的相同元素，并且在平台上放置至少两个宏的相同元素的共同元素。 宏的所有其他元素相对于公共元素放置在平台上的位置，以满足每个宏的宏放置规则。 可以通过识别多个宏中的相似元素并创建通用于相似元素的公共元素来识别相同元素。 用户设计一个金属化层以选择宏并配置所选宏的公共元素。
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2.发明授权Method and apparatus for use of hidden decoupling capacitors in an integrated circuit design 有权在集成电路设计中使用隐藏去耦电容器的方法和装置公开(公告)号：US07231625B2
公开(公告)日：2007-06-12
申请号：US10952194
申请日：2004-09-28
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A method and apparatus are provided for placing cells in an integrated circuit layout pattern. A base layer layout pattern defines an array of base cell locations and base layer elements, wherein at least portions of some rows in the array are reserved for decoupling capacitor cells. Each decoupling capacitor cell has a width, which is greater than that of a single base cell location and which is abstracted from the base layer layout pattern. A cell library defines a plurality of cells, including a macro cell having open rows consistent with the rows in the base layer layout pattern that are reserved for the decoupling capacitor cells. The width of each decoupling capacitor cell is abstracted from the macro cell. Cells from the cell library, including the macro cell, are placed within a design layout pattern relative to the base layer layout pattern. An area consumed by the macro cell within the design layout pattern is independent of the width of the decoupling capacitor cells.
摘要翻译： 提供了一种用于将电池放置在集成电路布局图案中的方法和装置。 基层布局图形定义基本单元位置和基层元素的阵列，其中阵列中的一些行的至少部分被保留用于去耦合电容器单元。 每个去耦电容器单元的宽度大于单个基本单元位置的宽度，并且从基层布局图案中抽取出来。 单元库定义多个单元，包括具有与为去耦电容器单元保留的基层布局图案中的行一致的开放行的宏单元。 每个去耦电容器单元的宽度从宏单元中抽象出来。 来自细胞库的细胞（包括宏细胞）相对于基底层布局图案被放置在设计布局图案内。 设计布局图案内宏单元消耗的面积与去耦电容单元的宽度无关。
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3.发明授权Method and apparatus for dynamic power management control using serial bus management protocols 有权使用串行总线管理协议进行动态电源管理控制的方法和装置公开(公告)号：US08312299B2
公开(公告)日：2012-11-13
申请号：US12411932
申请日：2009-03-26
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/325 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： An apparatus for on-demand power management includes an I/O serial communication master device, peripheral devices that communicate with the master device along the serial bus, and a power manager that buffers the peripheral devices from the serial communication master. The power manager also manages voltage regulation and clock sources to the peripheral devices, with the ability of placing the peripheral devices in an inactive state, or in any number of active states as a means to conserve energy. In some embodiments, the I/O serial communications master acts as if the peripheral devices are always in the highest activity state, and the power manager manages the communications to and from the peripheral devices and the power management of the peripheral devices to minimize energy consumption and reduce system latency.
摘要翻译： 用于按需电力管理的装置包括I / O串行通信主设备，沿着串行总线与主设备进行通信的外围设备以及从串行通信主设备缓冲外围设备的电源管理器。 电源管理器还管理外围设备的电压调节和时钟源，具有将外围设备置于无效状态或任何数量的活动状态作为节能手段的能力。 在一些实施例中，I / O串行通信主机的作用就好像外围设备始终处于最高活动状态，并且功率管理器管理与外围设备的通信和外围设备的电源管理以最小化能量消耗 并减少系统延迟。
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4.发明申请METHOD AND APPARATUS FOR DYNAMIC POWER MANAGEMENT CONTROL USING SERIAL BUS MANAGEMENT PROTOCOLS 审中-公开使用串行总线管理协议进行动态电力管理控制的方法和装置公开(公告)号：US20130061068A1
公开(公告)日：2013-03-07
申请号：US13666611
申请日：2012-11-01
IPC分类号： G06F1/26
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/325 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： An apparatus for on-demand power management including an I/O serial communication master device, peripheral devices that communicate with the master device along the serial communications bus, and a power manager that buffers the peripheral devices from the serial communication master. The power manager also manages voltage regulation and clock sources to the peripheral devices, with the ability of placing the peripheral devices in an inactive state, or in any number of active states as a means to conserve energy. In some embodiments, the I/O serial communications master acts as if the peripheral devices are always in the highest activity state, and the power manager manages the communications to and from the peripheral devices and the power management of the peripheral devices to reduce energy consumption and system latency.
摘要翻译： 一种用于按需电力管理的设备，包括I / O串行通信主设备，沿着串行通信总线与主设备通信的外围设备，以及从串行通信主站缓冲外围设备的电源管理器。 电源管理器还管理外围设备的电压调节和时钟源，具有将外围设备置于无效状态或任何数量的活动状态作为节能手段的能力。 在一些实施例中，I / O串行通信主机的作用就好像外围设备始终处于最高活动状态，并且功率管理器管理来自外围设备的通信和外围设备的通信以及外围设备的电源管理以降低能量消耗 和系统延迟。
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5.发明申请METHOD AND APPARATUS FOR DYNAMIC POWER MANAGEMENT CONTROL USING SERIAL BUS MANAGEMENT PROTOCOLS 有权使用串行总线管理协议进行动态电力管理控制的方法和装置公开(公告)号：US20090249089A1
公开(公告)日：2009-10-01
申请号：US12411932
申请日：2009-03-26
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/325 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： An apparatus for on-demand power management includes an I/O serial communication master device, peripheral devices that communicate with the master device along the serial bus, and a power manager that buffers the peripheral devices from the serial communication master. The power manager also manages voltage regulation and clock sources to the peripheral devices, with the ability of placing the peripheral devices in an inactive state, or in any number of active states as a means to conserve energy. In some embodiments, the I/O serial communications master acts as if the peripheral devices are always in the highest activity state, and the power manager manages the communications to and from the peripheral devices and the power management of the peripheral devices to minimize energy consumption and reduce system latency.
摘要翻译： 用于按需电力管理的装置包括I / O串行通信主设备，沿着串行总线与主设备进行通信的外围设备以及从串行通信主设备缓冲外围设备的电源管理器。 电源管理器还管理外围设备的电压调节和时钟源，具有将外围设备置于无效状态或任何数量的活动状态作为节能手段的能力。 在一些实施例中，I / O串行通信主机的作用就好像外围设备始终处于最高活动状态，并且功率管理器管理与外围设备的通信和外围设备的电源管理以最小化能量消耗 并减少系统延迟。
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6.发明授权公开(公告)号：US06662349B2
公开(公告)日：2003-12-09
申请号：US10086232
申请日：2002-02-27
IPC分类号： G06F1750
CPC分类号： G06F17/5068
摘要： A method of repeater insertion in a hierarchical integrated circuit includes defining an initial floorplan for a parent macro at a parent level in a hierarchical circuit design; passing outline and pin locations from the parent macro to a child macro sharing a common area with the parent macro; defining or modifying a floor plan for the child macro at a child level in the hierarchical circuit design in response to the outline and pin locations passed from the parent macro; passing physical restrictions in the child macro from the child macro to the parent macro; determining a location for a cell at the parent level of the hierarchical circuit design in an area of the parent macro shared by the child macro in response to the physical restrictions passed from the child macro; passing physical constraints in the parent macro associated with placement and routing of the cell from the parent level to the child macro; and generating an abstract representation for the child macro at the child level that includes an area cut out of the child macro corresponding to the location of the cell.
摘要翻译： 在分级集成电路中插入中继器的方法包括：在分级电路设计中，在父级别定义母宏的初始平面图; 将轮廓和引脚位置从父宏传递到与父宏共享公共区域的子宏; 响应于从父宏传送的轮廓和针位置，在分级电路设计中定义或修改子级别的子宏的平面图; 将子宏中的子宏中的物理限制从子宏传递到父宏; 响应于从所述子宏中传递的物理限制，在所述子宏宏共享的所述母宏的区域中确定所述分级电路设计的所述母级的单元的位置; 在与从父级别到子宏的单元的放置和路由相关联的父宏中传递物理约束; 以及生成子级别的子宏的抽象表示，该子宏包括从对应于该单元的位置的子宏中切出的区域。
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7.发明申请Synchronization of Position and Current Measurements in an Electric Motor Control Application using an FPGA 有权使用FPGA在电动机控制应用中的位置和电流测量的同步公开(公告)号：US20120217909A1
公开(公告)日：2012-08-30
申请号：US13280501
申请日：2011-10-25
申请人： Long Wu , Christopher J. Tremel , Kent D. Wanner
发明人： Long Wu , Christopher J. Tremel , Kent D. Wanner
CPC分类号： H02P21/04
摘要： A system and method for controlling an alternating current (AC) motor using a Field Programmable Gate Array (FPGA) to read the current and position measurements in an the AC motor, perform digital filtering of the position and current data, provide very precise synchronization of the measured phase current and position data, and output the data to a phase converter for control of the AC motor.
摘要翻译： 一种使用现场可编程门阵列（FPGA）控制交流（AC）电动机来读取AC电动机中的电流和位置测量的系统和方法，对位置和当前数据执行数字滤波，提供非常精确的同步 测量的相电流和位置数据，并将数据输出到用于控制交流电动机的相位转换器。
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