公开(公告)号：US06453063B1

公开(公告)日：2002-09-17

申请号：US09238435

申请日：1999-01-28

申请人： Michael Phaneuf ,  Dick James ,  Julia Elvidge ,  Pierrette Breton ,  Terry Ludlow ,  David Skoll ,  Bryan Socransky ,  Louise Weaver ,  Ray Haythornthwaite

发明人： Michael Phaneuf ,  Dick James ,  Julia Elvidge ,  Pierrette Breton ,  Terry Ludlow ,  David Skoll ,  Bryan Socransky ,  Louise Weaver ,  Ray Haythornthwaite

IPC分类号： G06K900

CPC分类号： G01N23/04 ,  G01N23/2258 ,  H01J2237/221 ,  H01J2237/226 ,  H01J2237/28

摘要： A method of imaging an integrated circuit using a focused ion beam system is presented. According to the method an integrated circuit is imaged in plan-view using a focused ion beam system. Circuit information is then extracted absent processing. In another embodiment, a method and system for imaging an entire IC automatically without removing the IC from the imaging system and requiring minimal operator intervention is presented. The method employs a focused ion beam system to image an exposed layer of an integrated circuit and then to etch a portion of the exposed layer in situ. Imaging and etching are repeated until substantially the entire integrated circuit is imaged. A processor is used to assemble the layers into a three-dimensional topography of the integrated circuit. Because of known relationships between layers, the mosaicing is facilitated and the final topography is more reliable than those produced by currently known computer implemented methods.

摘要翻译： 提出了一种使用聚焦离子束系统对集成电路进行成像的方法。 根据该方法，使用聚焦离子束系统在平面图中成像集成电路。 然后在没有处理的情况下提取电路信息。 在另一个实施例中，提出了一种用于自动成像整个IC而不从成像系统中移除IC并且需要最小的操作者干预的方法和系统。 该方法采用聚焦离子束系统来对集成电路的暴露层进行成像，然后原位蚀刻暴露层的一部分。 重复成像和蚀刻，直到基本上整个集成电路被成像。 处理器用于将层组装成集成电路的三维形貌。 由于层之间已知的关系，便于马赛克化，并且最终的形貌比目前已知的计算机实现的方法产生的形状更可靠。

公开(公告)号：US06288393B1

公开(公告)日：2001-09-11

申请号：US09238436

申请日：1999-01-28

申请人： Michael Phaneuf ,  Dick James ,  Pierrette Breton ,  Julia Elvidge ,  Ray Haythornthwaite

发明人： Michael Phaneuf ,  Dick James ,  Pierrette Breton ,  Julia Elvidge ,  Ray Haythornthwaite

IPC分类号： G01N23225

CPC分类号： G01N23/04 ,  G01N23/2258 ,  H01J2237/221 ,  H01J2237/226 ,  H01J2237/28

摘要： A method of analysing integrated circuits is provided. The method provides for scanning the integrated circuit with a beam in order to image an upper layer of the integrated circuit and performing chemical analysis on the upper layer of the integrated circuit. The chemical information and the imaging information are correlated and used to reverse engineer the integrated circuit.

摘要翻译： 提供了分析集成电路的方法。 该方法提供了用光束扫描集成电路，以便对集成电路的上层进行成像，并对集成电路的上层执行化学分析。 化学信息和成像信息相关并用于逆向工程集成电路。

公开(公告)号：US06684379B2

公开(公告)日：2004-01-27

申请号：US09927551

申请日：2001-08-13

申请人： David F. Skoll ,  Terry Ludlow ,  Julia Elvidge ,  Michael Phaneuf

发明人： David F. Skoll ,  Terry Ludlow ,  Julia Elvidge ,  Michael Phaneuf

IPC分类号： G06F1750

CPC分类号： G06T11/00 ,  G06T7/0002 ,  G06T7/0006 ,  G06T2200/24 ,  G06T2207/30148 ,  Y10S715/964

摘要： A design analysis workstation for performing design analysis of integrated circuits provides facilities for extracting design and layout information from digital image-mosaics captured during deconstruction of an integrated circuit. Each image-mosaic is displayed in at least one mosaic-view as a background image that is overlaid with at least one annotation overlay. An engineer analyst creates annotation objects on the annotation overlay based on information inferred concurrently from one or more image-mosaics. Concurrent display of a plurality of image-mosaics facilitates the understanding of interrelations between components on different layers. The design analysis workstation displays a plurality of cursors in respective views of mosaic-images, the cursors having lock-step motion to facilitate comprehension of the alignment of features on different concurrently displayed image-mosaics. The design analysis workstation provides facilities for performing operations on created annotation objects including grouping, cell definition, signal carrier creation, contact creation, signal propagation, net-list generation, etc. The advantages include annotation of image-mosaics using information derived from a plurality of concurrently displayed mosaic-views to facilitate tracing of interconnected busses and an understanding of interrelations between components.

摘要翻译： 用于执行集成电路设计分析的设计分析工作站提供从集成电路解构期间捕获的数字图像马赛克中提取设计和布局信息的设施。 每个图像马赛克以至少一个马赛克视图显示为覆盖有至少一个注释叠加层的背景图像。 工程师分析师根据从一个或多个图像马赛克同时推断的信息，在注释叠加层上创建注释对象。 并行显示多个图像马赛克有助于了解不同层上的组件之间的相互关系。 设计分析工作站在马赛克图像的各个视图中显示多个光标，光标具有锁步运动，以便于理解在不同的同时显示的图像马赛克上的特征对齐。 设计分析工作站提供用于对所创建的注释对象执行操作的设施，包括分组，小区定义，信号载体创建，联系创建，信号传播，网络列表生成等。优点包括使用从多个 同时显示马赛克视图，以便于跟踪互连的总线，并了解组件之间的相互关系。

公开(公告)号：US06641705B2

公开(公告)日：2003-11-04

申请号：US09818988

申请日：2001-03-27

申请人： Michael Phaneuf ,  Jian Li ,  Richard F. Shuman ,  Kathryn Noll ,  J. David Casey, Jr.

发明人： Michael Phaneuf ,  Jian Li ,  Richard F. Shuman ,  Kathryn Noll ,  J. David Casey, Jr.

IPC分类号： C23C1434

CPC分类号： G03F1/74 ,  H01J37/3056 ,  H01J2237/31744

摘要： A charged particle beam uniformly removes material, particularly crystalline material, from an area of a target by compensating for or altering the crystal orientation or structure of the material to be removed. The invention is particularly suited for FIB micromachining of copper-based crystalline structures. Uniformity of material removal can be improved, for example, by passing incoming ions through a sacrificial layer formed on the surface of the material to be removed. The sacrificial layer is removed along with the material being milled. Uniformity of removal can also be improved by changing the morphology of the material to be removed, for example, by disrupting its crystal structure or by altering its topography.

摘要翻译： 带电粒子束通过补偿或改变要去除的材料的晶体取向或结构来均匀地从靶的区域去除材料，特别是结晶材料。 本发明特别适用于铜基晶体结构的FIB微加工。 可以改善材料去除的均匀性，例如，通过将进入的离子通过形成在要去除的材料的表面上的牺牲层。 牺牲层与被研磨的材料一起被去除。 也可以通过改变要除去的材料的形态，例如通过破坏其晶体结构或改变其形貌来改善均匀性。