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1.发明授权Fault tolerance of data processing steps operating in either a parallel operation mode or a non-synchronous redundant operation mode 有权以并行操作模式或非同步冗余操作模式运行的数据处理步骤的容错公开(公告)号：US09052887B2
公开(公告)日：2015-06-09
申请号：US13577072
申请日：2010-02-16
CPC分类号： G06F9/28 , G06F9/38 , G06F11/1645 , G06F11/1695 , G06F2201/845
摘要： A method of processing data in a data processor comprising at least two data processing units. The method comprises performing different data processing steps in the data processing units concurrently during a parallel operation, and replicating performances of selected identical data processing steps in the data processing units during a non-synchronised redundant operation. The non-synchronised redundant operation comprises an initial performance of the selected identical data processing steps in one of the data processing units and a replicate performance of the data processing steps starting later than the initial performance, preferably in another of the data processing units. Initial result data representative of results from the initial performance are registered, and compared with replicate result data representative of results from the replicate performance, and an error signal is produced in case of discrepancy.
摘要翻译： 一种在包括至少两个数据处理单元的数据处理器中处理数据的方法。 该方法包括在并行操作期间同时在数据处理单元中执行不同的数据处理步骤，以及在非同步冗余操作期间在数据处理单元中复制所选择的相同数据处理步骤的性能。 非同步冗余操作包括在数据处理单元之一中所选择的相同数据处理步骤的初始性能以及优先于另一个数据处理单元中的初始性能开始的数据处理步骤的复制性能。 记录表示来自初始性能的结果的初始结果数据，并与代表复制性能的结果的复制结果数据进行比较，并且在差异的情况下产生错误信号。
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2.发明申请DATA PROCESSING METHOD, DATA PROCESSOR AND APPARATUS INCLUDING A DATA PROCESSOR 有权数据处理方法，数据处理器和包括数据处理器的设备公开(公告)号：US20120304024A1
公开(公告)日：2012-11-29
申请号：US13577072
申请日：2010-02-16
IPC分类号： G06F11/07
CPC分类号： G06F9/28 , G06F9/38 , G06F11/1645 , G06F11/1695 , G06F2201/845
摘要： A method of processing data in a data processor comprising at least two data processing units. The method comprises performing different data processing steps in the data processing units concurrently during a parallel operation, and replicating performances of selected identical data processing steps in the data processing units during a non-synchronised redundant operation. The non-synchronised redundant operation comprises an initial performance of the selected identical data processing steps in one of the data processing units and a replicate performance of the data processing steps starting later than the initial performance, preferably in another of the data processing units. Initial result data representative of results from the initial performance are registered, and compared with replicate result data representative of results from the replicate performance, and an error signal is produced in case of discrepancy.
摘要翻译： 一种在包括至少两个数据处理单元的数据处理器中处理数据的方法。 该方法包括在并行操作期间同时在数据处理单元中执行不同的数据处理步骤，以及在非同步冗余操作期间在数据处理单元中复制所选择的相同数据处理步骤的性能。 非同步冗余操作包括在数据处理单元之一中所选择的相同数据处理步骤的初始性能以及优先于另一个数据处理单元中的初始性能开始的数据处理步骤的复制性能。 记录表示来自初始性能的结果的初始结果数据，并与代表复制性能的结果的复制结果数据进行比较，并且在差异的情况下产生错误信号。
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3.发明授权Method for automated managing of the usage of alternative code and a processing system of operating thereof 有权用于自动管理替代代码的使用的方法及其操作的处理系统公开(公告)号：US09430230B2
公开(公告)日：2016-08-30
申请号：US14459419
申请日：2014-08-14
申请人： Tobias Thiel , Markus Regner , Michael Rohleder
发明人： Tobias Thiel , Markus Regner , Michael Rohleder
IPC分类号： G06F9/44
CPC分类号： G06F8/71 , G06F8/36 , G06F8/73 , G06F17/5045
摘要： The present application relates to a method and a processing system for automated managing of the usage of alternative code. Code sections including original code and alternative code are retrieved from a code basis and the retrieved code is analyzed to detect an alternative code section. A condition definition associated with the identified alternative code section is further retrieved and the condition of the retrieved condition definition is evaluated. The identified alternative code section is activated in accordance with the evaluation result.
摘要翻译： 本申请涉及用于自动管理替代代码的使用的方法和处理系统。 从代码基础中检索包括原始代码和替代代码的代码段，并分析检索到的代码以检测替代代码段。 进一步检索与识别的替代代码部分相关联的条件定义，并且评估检索到的条件定义的条件。 识别的替代代码部分根据评估结果被激活。
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4.发明授权Synchronous circuit, method of designing a synchronous circuit, and method of validating a synchronous circuit 有权同步电路，同步电路的设计方法以及同步电路的验证方法公开(公告)号：US09244123B1
公开(公告)日：2016-01-26
申请号：US14552543
申请日：2014-11-25
申请人： Thomas Koch , Ilhan Hatirnaz , Michael Rohleder
发明人： Thomas Koch , Ilhan Hatirnaz , Michael Rohleder
IPC分类号： G06F17/50 , G01R31/317 , G01R31/3177
CPC分类号： G01R31/31726 , G01R31/31727 , G01R31/3177 , G06F17/505
摘要： A synchronous circuit comprises a functional circuitry and one or more validation circuits for validating synchronization of the functional circuitry. The functional and the validation circuits are clocked by a clock source. Each validation circuit comprises a clock distribution network, a test signal generator, a capture cell, a test signal path from the test signal generator to the capture cell, and a verification unit. The clock distribution network applies a launch clock signal at the test signal generator and a capture clock signal at the capture cell. The test signal generator produces a bi-level test signal. The test signal path transmits the test signal to the capture cell, which generates a proof sequence by sampling the test signal. The verification unit determines whether the proof sequence is identical to the test sequence.A method of designing a synchronous circuit and method of validating a synchronous circuit are also described.
摘要翻译： 同步电路包括功能电路和用于验证功能电路的同步的一个或多个确认电路。 功能和验证电路由时钟源提供时钟。 每个验证电路包括时钟分配网络，测试信号发生器，捕获单元，从测试信号发生器到捕获单元的测试信号路径，以及验证单元。 时钟分配网络在测试信号发生器处应用发射时钟信号，并在捕捉单元处施加捕获时钟信号。 测试信号发生器产生双电平测试信号。 测试信号路径将测试信号发送到捕获单元，其通过对测试信号进行采样来产生校验序列。 验证单元确定验证序列是否与测试序列相同。 还描述了设计同步电路的方法和验证同步电路的方法。
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公开(公告)号：US09024663B2
公开(公告)日：2015-05-05
申请号：US14015519
申请日：2013-08-30
IPC分类号： H03K5/19 , H03K9/06 , G06F1/04 , H03K5/1252
CPC分类号： G06F1/04 , H03K5/1252
摘要： In a first circuit for detecting clock glitches in a clock signal, a master counter is clocked by the clock signal and memorizes a master count. An incrementer advances the master count by one increment. A slave counter is clocked by the clock signal and memorizes a slave count. The slave count is retarded relative to the master count by at least a particular number of clock edges. A comparator determines whether the difference between the master count and the slave count is at least a value of the incrementer times the particular number of clock edges.
摘要翻译： 在用于检测时钟信号中的时钟毛刺的第一电路中，主计数器由时钟信号计时，并存储主计数。 增量器将主计数递增一个增量。 从计数器由时钟信号计时，并存储从计数。 从计数相对于主计数延迟至少一定数量的时钟沿。 比较器确定主计数和从计数之间的差是否至少是递增器的值乘以特定数量的时钟边沿。
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6.发明授权Processor based system having ECC based check and access validation information means 有权具有基于ECC的检查和访问验证信息的基于处理器的系统意味着公开(公告)号：US08650440B2
公开(公告)日：2014-02-11
申请号：US12811454
申请日：2008-01-16
申请人： Michael Rohleder , Gary Hay , Stephan Mueller , Manfred Thanner
发明人： Michael Rohleder , Gary Hay , Stephan Mueller , Manfred Thanner
IPC分类号： G06F11/00
CPC分类号： G06F11/1645 , G06F11/10 , G06F11/1654 , G06F2201/845
摘要： A system comprises a first master element; and at least one shared communication element arranged to operably couple the first master element to at least one slave element. The system further comprises at least one validation element located on at least one further validation path located between the first master element and the at least one slave element, wherein the at least one validation element is arranged to validate at least one of: at least one access request by the first master element; and a response to an access request from the at least one slave element.
摘要翻译： 一种系统包括第一主元件; 以及布置成将第一主元件可操作地耦合到至少一个从属元件的至少一个共享通信元件。 所述系统还包括位于位于所述第一主元件和所述至少一个从属元件之间的至少一个另外的验证路径上的至少一个验证元件，其中所述至少一个验证元件被布置成验证以下至少一个：至少一个 由第一个主元素访问请求; 以及对来自所述至少一个从属单元的访问请求的响应。
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公开(公告)号：US20100058144A1
公开(公告)日：2010-03-04
申请号：US12515242
申请日：2006-11-21
申请人： Michael Rohleder , Davor Bogavac
发明人： Michael Rohleder , Davor Bogavac
CPC分类号： G06F11/1008 , G06F11/1016 , G06F11/1024 , G11C2029/1208 , G11C2029/4402 , H03M13/151
摘要： A memory system including a first memory for storing data and an ECC unit for accessing the first memory and for detecting errors in data retrieved from the first memory, and characterised by an error further processing arrangement operable to process errors detected by the ECC unit, the error further processing arrangement including a second memory for recording information relating to the detected errors.Also described is a method of operation in the memory system.
摘要翻译： 一种包括用于存储数据的第一存储器和用于访问第一存储器的ECC单元并且用于检测从第一存储器检索的数据中的错误的存储器系统，其特征在于可操作以处理由ECC单元检测到的错误的错误进一步处理装置， 错误的进一步处理布置包括用于记录与检测到的错误有关的信息的第二存储器。 还描述了存储系统中的操作方法。
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8.发明授权Error correcting device, method for monitoring an error correcting device and data processing system 有权纠错装置，用于监视纠错装置和数据处理系统的方法公开(公告)号：US09246512B2
公开(公告)日：2016-01-26
申请号：US13988821
申请日：2010-12-02
CPC分类号： H03M13/05 , G06F11/0754 , G06F11/0757 , G06F11/0766 , G06F11/0772 , G06F11/1048
摘要： An error correcting device is provided that has an input connectable to receive one or more data units, an error detection module arranged to identify a presence of one or more errors in a received data unit of the one or more data units and to provide an error detection signal for the received data unit, an error correction module arranged to perform an error correction processing on the received data unit and provide a corrected data unit, and a correction evaluation module arranged to perform a comparison of the received data unit with the corrected data unit and to generate a correction error signal depending on a result of the comparison and the error detection signal.
摘要翻译： 提供了一种错误校正装置，其具有可连接以接收一个或多个数据单元的输入;错误检测模块，被布置为识别所述一个或多个数据单元的接收数据单元中存在一个或多个错误，并提供错误 用于接收数据单元的检测信号;纠错模块，被配置为对所接收的数据单元执行纠错处理，并提供校正数据单元;以及校正评估模块，被配置为执行所接收数据单元与校正数据的比较 并根据比较结果和误差检测信号产生校正误差信号。
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9.发明授权System for dynamically distributing an available memory resource to redundant and non-redundant storage areas using RAM routing logic 有权使用RAM路由逻辑将可用内存资源动态分配到冗余和非冗余存储区域的系统公开(公告)号：US09152511B2
公开(公告)日：2015-10-06
申请号：US12995317
申请日：2008-06-20
申请人： Michael Rohleder , Gary Hay , Stephan Mueller , Manfred Thanner
发明人： Michael Rohleder , Gary Hay , Stephan Mueller , Manfred Thanner
CPC分类号： G06F11/1666 , G06F11/1629 , G06F11/167 , G06F2201/845 , G11C7/1075 , G11C29/74 , G11C2029/0411
摘要： A system for distributing an available memory resource comprising at least two random access memory (RAM) elements and RAM routing logic. The RAM routing logic comprises configuration logic to dynamically distribute the available memory resource into a first memory area providing redundant memory storage and a second memory area providing non-redundant memory storage. The system may further comprise bus access ports which support at least one of concurrent access by a bus access port to access redundantly stored data or non-redundantly stored data, or concurrent access by at least two bus access ports to respective RAM elements to access redundantly stored data or to a respective one of the RAM elements to access non-redundantly stored data. Comparison logic and error detection or correction logic may be provided to detect or correct errors in information read from the RAM elements.
摘要翻译： 一种用于分发包括至少两个随机存取存储器（RAM）元件和RAM路由逻辑的可用存储器资源的系统。 RAM路由逻辑包括用于动态地将可用存储器资源分配到提供冗余存储器存储器的第一存储器区域和提供非冗余存储器存储器的第二存储器区域的配置逻辑。 该系统还可以包括总线访问端口，其支持总线访问端口的并发访问中的至少一个以访问冗余存储的数据或非冗余存储的数据，或者由至少两个总线访问端口到相应的RAM元件的并发访问以冗余访问 存储数据或RAM元素中的相应一个以访问非冗余存储的数据。 可以提供比较逻辑和错误检测或校正逻辑来检测或纠正从RAM元件读取的信息中的错误。
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公开(公告)号：US08552764B2
公开(公告)日：2013-10-08
申请号：US13131349
申请日：2009-01-05
CPC分类号： G06F1/04 , H03K5/1252
摘要： In a first circuit for detecting clock glitches in a clock signal, a master counter is clocked by the clock signal and memorizes a master count. An incrementer advances the master count by one increment. A slave counter is clocked by the clock signal and memorizes a slave count. The slave count is retarded relative to the master count by at least a particular number of clock edges. A comparator determines whether the difference between the master count and the slave count is at least a value of the incrementer times the particular number of clock edges.
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