公开(公告)号：US07293196B2

公开(公告)日：2007-11-06

申请号：US10434489

申请日：2003-05-07

申请人： Michael S. Hicken ,  James N. Snead

发明人： Michael S. Hicken ,  James N. Snead

IPC分类号： G06F12/16 ,  G06F12/08

CPC分类号： G06F11/2092 ,  G06F11/1666 ,  G06F11/20 ,  G06F11/2097 ,  G06F12/0866

摘要： A method, apparatus, and system for preserving the cache data of redundant storage controllers, by copying the recorded data blocks and the associated cache tags in the primary cache memory of a storage controller to a secondary cache memory of an alternate, redundant storage controller, wherein upon a failure occurring in the primary cache memory of any of the storage controllers, subsequent storage requests from a host, previously intended for processing by the failed storage controller, are processed through the secondary cache memory of a non-failed, redundant storage controller that contains the failed storage's controller cache data and cache tags.

摘要翻译： 通过将存储控制器的主高速缓冲存储器中记录的数据块和相关联的高速缓存标签复制到备用冗余存储控制器的二次高速缓冲存储器来保存冗余存储控制器的高速缓存数据的方法，装置和系统， 其中当在任何存储控制器的主高速缓冲存储器中发生故障时，先前由故障存储控制器进行处理的来自主机的后续存储请求通过非故障冗余存储控制器的二次高速缓冲存储器来处理 它包含失败的存储的控制器缓存数据和缓存标签。

公开(公告)号：US20100287320A1

公开(公告)日：2010-11-11

申请号：US12436227

申请日：2009-05-06

申请人： Carlos Querol ,  James N. Snead ,  Michael S. Hicken ,  Randal S. Rysavy ,  Carl E. Forhan

发明人： Carlos Querol ,  James N. Snead ,  Michael S. Hicken ,  Randal S. Rysavy ,  Carl E. Forhan

IPC分类号： G06F9/46 ,  G06F13/24 ,  G06F15/76 ,  G06F9/06

CPC分类号： G06F9/544

摘要： Described embodiments provide interprocessor communication between at least two processors of an integrated circuit, each processor running at least one task. For each processor, a proxy task is generated corresponding to each task running on each other processor. A task identifier for each task, and a look-up table having each task identifier associated with each other processor running the task is also generated. When a message is sent from a source task to a destination task that is running on a different processor than the source task, the source task communicates with the proxy task of the destination task. The proxy task appends the task identifier for the destination task to the message and sends the message to an interprocessor communication interface. Based on the task identifier, the processor running the destination task is determined and the destination task retrieves the message.

摘要翻译： 所描述的实施例提供集成电路的至少两个处理器之间的处理器间通信，每个处理器运行至少一个任务。 对于每个处理器，生成对应于在每个其他处理器上运行的每个任务的代理任务。 还产生每个任务的任务标识符以及具有与运行任务的每个其他处理器相关联的每个任务标识符的查找表。 当从源任务发送消息到与源任务不同的处理器上运行的目标任务时，源任务与目标任务的代理任务进行通信。 代理任务将目标任务的任务标识符附加到消息中，并将消息发送到处理器间通信接口。 基于任务标识符，确定运行目标任务的处理器，并且目的地任务检索该消息。

公开(公告)号：US08448029B2

公开(公告)日：2013-05-21

申请号：US12401669

申请日：2009-03-11

申请人： James N. Snead

发明人： James N. Snead

IPC分类号： G06F11/00

CPC分类号： G06F13/24 ,  G06F11/0724 ,  G06F11/0757 ,  G06F11/0793

摘要： A multiprocessor system with multiple watchdog timers, the timers causing all the processors in the system to concurrently process a common interrupt signal asserted by any of the watchdog timers timing out. The processors, in response to the common interrupt signal, store data residing in their local memories into a memory common to all the processors. The stored data is then stored in a permanent storage device for later analysis. Thereafter, all of the processors are reset.

摘要翻译： 具有多个看门狗定时器的多处理器系统，定时器使系统中的所有处理器同时处理由任何看门狗定时器超时所确定的公共中断信号。 处理器响应于公共中断信号将驻留在其本地存储器中的数据存储到所有处理器公用的存储器中。 然后将存储的数据存储在永久存储设备中以供以后分析。 此后，所有处理器都被复位。

公开(公告)号：US20100235558A1

公开(公告)日：2010-09-16

申请号：US12401669

申请日：2009-03-11

申请人： James N. Snead

发明人： James N. Snead

IPC分类号： G06F13/24

CPC分类号： G06F13/24 ,  G06F11/0724 ,  G06F11/0757 ,  G06F11/0793

摘要： A multiprocessor system with multiple watchdog timers, the timers causing all the processors in the system to concurrently process a common interrupt signal asserted by any of the watchdog timers timing out. The processors, in response to the common interrupt signal, store data residing in their local memories into a memory common to all the processors. The stored data is then stored in a permanent storage device for later analysis. Thereafter, all of the processors are reset.

摘要翻译： 具有多个看门狗定时器的多处理器系统，定时器使系统中的所有处理器同时处理由任何看门狗定时器超时所确定的公共中断信号。 处理器响应于公共中断信号将驻留在其本地存储器中的数据存储到所有处理器公用的存储器中。 然后将存储的数据存储在永久存储设备中以供以后分析。 此后，所有处理器都被复位。

公开(公告)号：US07162587B2

公开(公告)日：2007-01-09

申请号：US10430487

申请日：2003-05-05

申请人： Michael S. Hiken ,  Steven M. Howe ,  James N. Snead

发明人： Michael S. Hiken ,  Steven M. Howe ,  James N. Snead

IPC分类号： G06F15/177

CPC分类号： G06F11/2092 ,  G06F11/1658 ,  G06F11/2089 ,  G06F12/0866

摘要： A method, and apparatus for recovering cache data of a failed redundant storage controller and reestablishing redundancy by mirroring cache data of a primary cache memory of a first storage controller in a secondary cache memory of another storage controller. Upon a failure occurring in a storage controller, the failure is detected and, in response, a structured list of cache tags is created in the controller where having the secondary cache that is the mirror of the primary cache of the failed controller. The primary cache memory of the non-failed storage controller that was mirrored in the secondary cache of the failed controller and the secondary cache memory of the non-failed storage controller that was linked to the primary cache of the failed controller are flushed, and an available secondary cache memory, which may be the secondary cache memory just flushed, is configured to function as a redundant cache memory for the primary cache memory of the non-failed storage controller that was mirrored in the secondary cache of the failed controller, such that cache data in the primary cache memory of the non-failed storage controller is mirrored in the available secondary cache memory.

摘要翻译： 一种用于恢复故障冗余存储控制器的高速缓存数据的方法和装置，并且通过镜像另一存储控制器的二级高速缓冲存储器中的第一存储控制器的主高速缓存存储器的高速缓存数据来重新建立冗余。 在存储控制器中发生故障时，检测到故障，并且作为响应，在控制器中创建高速缓存标签的结构化列表，其中具有作为故障控制器的主高速缓存的镜像的二级高速缓存。 被镜像在故障控制器的二级缓存中的非故障存储控制器的主缓存内存和链接到失败控制器的主缓存的非故障存储控制器的辅助缓存内存被刷新，并且 被配置为作为在故障控制器的二级高速缓存中被镜像的非故障存储控制器的主高速缓冲存储器的冗余高速缓冲存储器的可用次级高速缓存存储器，其可以是刚被刷新的二次高速缓存存储器，使得 非故障存储控制器的主高速缓冲存储器中的高速缓存数据被镜像到可用的二级高速缓冲存储器中。