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1.发明授权Computer system and method for evaluating predicates and Boolean expressions 失效用于评估谓词和布尔表达式的计算机系统和方法
公开(公告)号：US6023751A
公开(公告)日：2000-02-08
申请号：US400414
申请日：1995-03-03
CPC分类号： G06F9/30029 , G06F7/00
摘要： A computer system provides fast evaluation of predicates and Boolean expressions with a set of operations for determining a value in a specified register from a plurality of inputs. The execution of each operation is defined by two functions of the operation's inputs: a result function which yields a result value, and an enable function which determines whether the result value is written to the specified register. To evaluate a Boolean expression with the operations, the register is preset to a Boolean value, e.g. one for an AND reduction, zero for an OR reduction. The operations can then write a Boolean value, e.g. zero for an AND reduction, one for an OR reduction, to the register if each operation's enable function evaluates true. The register then stores the correct value of the expression. The expression's value can be used as predicates to conditionally execute operations in a program. Preferably, the operations are executed in parallel by plural functional units, and the register is capable of accepting multiple values written simultaneously, so long as they are identical.
摘要翻译： 计算机系统通过一组用于从多个输入中确定指定寄存器中的值的操作来提供对谓词和布尔表达式的快速评估。 每个操作的执行由操作输入的两个功能定义：产生结果值的结果函数和确定结果值是否写入指定寄存器的使能函数。 要使用这些操作来评估一个布尔表达式，寄存器被预置为布尔值，例如。 一个用于和减少，零减少OR。 然后，操作可以写一个布尔值，例如 如果每个操作的启用功能评估为真，则为零减少一个用于OR减少的零。 寄存器然后存储表达式的正确值。 表达式的值可以用作谓词来有条件地执行程序中的操作。 优选地，这些操作由多个功能单元并行执行，并且寄存器能够接受同时写入的多个值，只要它们相同即可。
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公开(公告)号：US5664135A
公开(公告)日：1997-09-02
申请号：US313980
申请日：1994-09-28
CPC分类号： G06F9/30163 , G06F9/30058 , G06F9/3806
摘要： An improved computer architecture and instruction set that reduces the delays produced by branch instructions. The invention utilizes a branch processor having a branch memory for storing information specifying a plurality of branch instructions that are contained in a code sequence. The branch memory stores information specifying the target address of each branch instruction and the location of the branch instruction with respect to the beginning of the code sequence. The branch processor receives the results of the various comparisons that determine if the conditions associated with the various branches stored in the branch memory are satisfied. The branch processor preferably stores the identity of the branch that is closed to the beginning of the code sequence for which the condition associated therewith has been satisfied. This branch will be referred to as the highest branch enabled. The actual branching operation is carded out in response to the receipt of an execute branch instruction which specifies one or more of the branches stored in the branch memory. If one of the branches specified in the execute branch instruction matches the highest branch enabled, then the code sequence continues at the target address of the highest branch enabled.
摘要翻译： 改进的计算机体系结构和指令集，减少了分支指令产生的延迟。 本发明利用具有分支存储器的分支处理器，用于存储指定包含在代码序列中的多个分支指令的信息。 分支存储器存储指定每个分支指令的目标地址的信息和关于代码序列的开始的分支指令的位置。 分支处理器接收确定与分支存储器中存储的各种分支相关联的条件是否满足的各种比较的结果。 分支处理器优选地存储已经满足与其相关联的条件的代码序列的开始处的关闭的分支的标识。 该分支将被称为启用最高分支。 响应于接收到指定分支存储器中存储的一个或多个分支的执行分支指令，梳理出实际分支操作。 如果在执行分支指令中指定的分支之一与启用的最高分支匹配，则代码序列在启用的最高分支的目标地址处继续。
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公开(公告)号：US5999738A
公开(公告)日：1999-12-07
申请号：US964050
申请日：1997-11-06
IPC分类号： G06F9/45
CPC分类号： G06F8/445
摘要： A technique for flexible scheduling of a code sequence wherein a set of instructions for determining a a fully-resolved predicate for each of a set of non-speculative instructions contained in the code sequence is generated. An optimized code sequence is then generated that includes the instructions for determining the fully resolved predicates and that further includes the non-speculative instructions each guarded by one of the fully resolved predicates such that any one of the non-speculative instructions may be executed before any other of the non-speculative instructions.
摘要翻译： 一种用于编码序列的灵活调度的技术，其中生成用于为包含在码序列中的一组非推测性指令中的每一个确定完全解析谓词的一组指令。 然后生成优化的代码序列，其包括用于确定完全解析的谓词的指令，并且还包括每个由完全解析的谓词之一保护的非推测性指令，使得任何一个非推测性指令可以在任何 其他非投机性指示。
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公开(公告)号：US5850553A
公开(公告)日：1998-12-15
申请号：US747054
申请日：1996-11-12
IPC分类号： G06F9/45
摘要： A compiler technique for reducing the number of executed branches in a code sequence. Multiple condition branch instructions in a program sequence are replaced with a single combined conditional branch instruction thereby eliminating the time-consuming execution of multiple branch instructions by a target processor.
摘要翻译： 一种用于减少代码序列中执行分支数量的编译器技术。 程序序列中的多条件分支指令被替换为单个组合条件分支指令，从而消除了目标处理器对多个分支指令的耗时执行。
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