公开(公告)号：US07203916B2

公开(公告)日：2007-04-10

申请号：US10602369

申请日：2003-06-24

申请人： Michael W. Dotson ,  Matthew D. Wise

发明人： Michael W. Dotson ,  Matthew D. Wise

IPC分类号： G06F17/50

CPC分类号： G06F17/5072 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2924/00

摘要： Under the present invention, a proposed placement of I/O pads into one or more groups on a chip analyzed. Specifically, using resources such as a control file, cross-reference table, an I/O limit table, and an optional information file, a group switching current for each proposed I/O pad group is automatically calculated and compared to predetermined maximum switching current(s). If an I/O pad group exhibits a switching current that exceeds its predetermined maximum, corrective action is taken. Such action can include, for example, relocation of an I/O pad from an overloaded I/O pad group to another I/O pad group, insertion of an additional power pad into the overloaded I/O pad group, etc.

摘要翻译： 在本发明中，提出将I / O焊盘放置在分析的芯片上的一个或多个组中。 具体地，使用诸如控制文件，交叉引用表，I / O限制表和可选信息文件的资源，自动计算每个所提出的I / O焊盘组的组切换电流，并将其与预定的最大开关电流 （s）。 如果I / O焊盘组显示超过其预定最大值的开关电流，则采取纠正措施。 这样的动作可以包括例如将I / O焊盘从过载的I / O焊盘组重定位到另一个I / O焊盘组，将额外的功率垫插入到过载的I / O焊盘组等中。

公开(公告)号：US08020134B2

公开(公告)日：2011-09-13

申请号：US12035950

申请日：2008-02-22

申请人： Michael W. Dotson ,  Anthony DeGroff Drumm ,  Dazhuang J. Ma ,  Ruchir Puri ,  Louise H. Trevillyan

发明人： Michael W. Dotson ,  Anthony DeGroff Drumm ,  Dazhuang J. Ma ,  Ruchir Puri ,  Louise H. Trevillyan

IPC分类号： G06F17/50

CPC分类号： G06F17/5045

摘要： In one embodiment, the invention is a method and apparatus for parallel processing of semiconductor chip designs. One embodiment of a method for processing a semiconductor chip design includes flattening a netlist corresponding to the semiconductor chip design, performing logic clustering on one or more logic elements incorporated in the flattened netlist to generate one or more clusters, partitioning the semiconductor chip design in accordance with the one or more clusters, and designing the individual partitions in parallel.

摘要翻译： 在一个实施例中，本发明是用于半导体芯片设计的并行处理的方法和装置。 用于处理半导体芯片设计的方法的一个实施例包括平坦化对应于半导体芯片设计的网表，对并入在扁平化网表中的一个或多个逻辑元件执行逻辑聚类以生成一个或多个簇，根据该划分半导体芯片设计 使用一个或多个集群，并且并行设计各个分区。

公开(公告)号：US20090271752A1

公开(公告)日：2009-10-29

申请号：US12108599

申请日：2008-04-24

申请人： Charles J. Alpert ,  Michael W. Dotson ,  Gi-Joon Nam ,  Shyam Ramji ,  Natarajan Viswanathan

发明人： Charles J. Alpert ,  Michael W. Dotson ,  Gi-Joon Nam ,  Shyam Ramji ,  Natarajan Viswanathan

IPC分类号： G06F17/50

CPC分类号： G06F17/5072

摘要： A hierarchical method of legalizing the placement of logic cells in the presence of blockages selectively classifies the blockages into at least two different sets based on size (large and small). Movable logic cells are relocated first among coarse regions between large blockages to remove overlaps among the cells and the large blockages without regard to small blockages (while satisfying capacity constraints of the coarse regions), and thereafter the movable logic cells are relocated among fine regions between small blockages to remove all cell overlaps (while satisfying capacity constraints of the fine regions). The coarse and fine regions may be horizontal slices of the placement region having a height corresponding to a single circuit row height of the design. Cells are relocated with minimal perturbation from the previous placement, preserving wirelength and timing optimizations. The legalization technique may utilize more than two levels of granularity with multiple relocation stages.

摘要翻译： 在存在阻塞的情况下使逻辑单元的放置合法化的分级方法根据大小（大和小）选择性地将阻塞分类为至少两个不同的集合。 可移动逻辑单元首先在大阻塞之间的粗略区域中重新定位，以消除单元和大阻塞之间的重叠，而不考虑小的阻塞（同时满足粗略区域的容量约束），然后将可移动逻辑单元重新定位在 小的堵塞以消除所有的细胞重叠（同时满足精细区域的容量限制）。 粗细区域可以是具有对应于设计的单个电路行高度的高度的放置区域的水平切片。 细胞被重新定位，从最初的位置移动，保持线长和时序优化。 合法化技术可以利用具有多个重定位阶段的多于两个级别的粒度。

公开(公告)号：US07934188B2

公开(公告)日：2011-04-26

申请号：US12108599

申请日：2008-04-24

申请人： Charles J. Alpert ,  Michael W. Dotson ,  Gi-Joon Nam ,  Shyam Ramji ,  Natarajan Viswanathan

发明人： Charles J. Alpert ,  Michael W. Dotson ,  Gi-Joon Nam ,  Shyam Ramji ,  Natarajan Viswanathan

IPC分类号： G06F17/50

CPC分类号： G06F17/5072

摘要： A hierarchical method of legalizing the placement of logic cells in the presence of blockages selectively classifies the blockages into at least two different sets based on size (large and small). Movable logic cells are relocated first among coarse regions between large blockages to remove overlaps among the cells and the large blockages without regard to small blockages (while satisfying capacity constraints of the coarse regions), and thereafter the movable logic cells are relocated among fine regions between small blockages to remove all cell overlaps (while satisfying capacity constraints of the fine regions). The coarse and fine regions may be horizontal slices of the placement region having a height corresponding to a single circuit row height of the design. Cells are relocated with minimal perturbation from the previous placement, preserving wirelength and timing optimizations. The legalization technique may utilize more than two levels of granularity with multiple relocation stages.

摘要翻译： 在存在阻塞的情况下使逻辑单元的放置合法化的分级方法根据大小（大和小）选择性地将阻塞分类为至少两个不同的集合。 可移动逻辑单元首先在大阻塞之间的粗略区域中重新定位，以消除单元和大阻塞之间的重叠，而不考虑小的阻塞（同时满足粗略区域的容量约束），然后将可移动逻辑单元重新定位在 小的堵塞以消除所有的细胞重叠（同时满足精细区域的容量限制）。 粗细区域可以是具有对应于设计的单个电路行高度的高度的放置区域的水平切片。 细胞被重新定位，从最初的位置移动，保持线长和时序优化。 合法化技术可以利用具有多个重定位阶段的多于两个级别的粒度。