摘要:
A method and apparatus for clock signal noise shaping are described. Embodiments of a clock circuit include a filter coupled to receive an input clock signal and to provide an output clock signal. The filter filters noise of the input clock signal to shape the noise to provide the output clock signal. In a method for adjustment of phase noise, input clock signaling having the phase noise is obtained, and the input clock signal is filtered to adjust the phase noise to provide output clock signaling.
摘要:
An embodiment of a method for powering a low-power device using a power supply designed for a high-power device is described. In such an embodiment, an input voltage is provided to a voltage converter at a first voltage level. The input voltage is periodically electrically coupled to and decoupled from the voltage converter during operation of the low-power device. An output voltage is output from the voltage converter at a second voltage level to power the low-power device. The output voltage is provided during both the input voltage being electrically coupled to and decoupled from the voltage converter, and the second voltage level is substantially less than the first voltage level.
摘要:
Embodiments of an apparatus for signal conditioning, a serial data interface, and a method for a programmable delay filter are disclosed. In an embodiment of an apparatus for signal conditioning, a wave shaping circuit has a precursor signal, a post cursor signal, and a main signal combined to provide an output signal. The precursor signal, the post cursor signal, and the main signal are provided for combination independently of a clock signal. The main signal is delayed relative to the precursor signal, and the post cursor signal is delayed relative to the main signal.
摘要:
Method and apparatus for a communication system (100) using a driver block (200) are described. The driver block includes memory having programmable non-volatile memory cells for storing configuration settings associated with operation of the driver block (200). The driver block (200) is programmable for a selected interface protocol for operation in an adaptive equalization mode to obtain an adaptive equalization value. The adaptive equalization value is stored as a fixed equalization value for operating the driver block in a fixed equalization mode. The driver block may be used as a serial link driver interface.