Clock signal noise shaping
    1.
    发明授权
    Clock signal noise shaping 有权
    时钟信号噪声整形

    公开(公告)号:US08044711B1

    公开(公告)日:2011-10-25

    申请号:US12704150

    申请日:2010-02-11

    IPC分类号: H03B1/00

    CPC分类号: H03L7/16

    摘要: A method and apparatus for clock signal noise shaping are described. Embodiments of a clock circuit include a filter coupled to receive an input clock signal and to provide an output clock signal. The filter filters noise of the input clock signal to shape the noise to provide the output clock signal. In a method for adjustment of phase noise, input clock signaling having the phase noise is obtained, and the input clock signal is filtered to adjust the phase noise to provide output clock signaling.

    摘要翻译: 描述了时钟信号噪声整形的方法和装置。 时钟电路的实施例包括耦合以接收输入时钟信号并提供输出时钟信号的滤波器。 滤波器滤除输入时钟信号的噪声,以形成噪声,以提供输出时钟信号。 在调节相位噪声的方法中,获得具有相位噪声的输入时钟信号,并且对输入时钟信号进行滤波以调整相位噪声以提供输出时钟信号。

    Voltage conversion
    2.
    发明授权
    Voltage conversion 有权
    电压转换

    公开(公告)号:US08400183B1

    公开(公告)日:2013-03-19

    申请号:US13008328

    申请日:2011-01-18

    IPC分类号: H03K19/0175

    摘要: An embodiment of a method for powering a low-power device using a power supply designed for a high-power device is described. In such an embodiment, an input voltage is provided to a voltage converter at a first voltage level. The input voltage is periodically electrically coupled to and decoupled from the voltage converter during operation of the low-power device. An output voltage is output from the voltage converter at a second voltage level to power the low-power device. The output voltage is provided during both the input voltage being electrically coupled to and decoupled from the voltage converter, and the second voltage level is substantially less than the first voltage level.

    摘要翻译: 描述了使用为高功率设备设计的电源为低功率设备供电的方法的实施例。 在这样的实施例中,输入电压以第一电压电平提供给电压转换器。 在低功率器件的工作期间,输入电压周期性地电耦合到电压转换器并从电压转换器去耦。 输出电压从电压转换器以第二电压电平输出,为低功率器件供电。 在两个输入电压都被电耦合到电压转换器和从电压转换器去耦之间提供输出电压,而第二电压电平基本上小于第一电压电平。

    Signal conditioning by combining precursor, main, and post cursor signals without a clock signal
    3.
    发明授权
    Signal conditioning by combining precursor, main, and post cursor signals without a clock signal 有权
    通过组合前体,主和后光标信号而无需时钟信号进行信号调理

    公开(公告)号:US08755474B2

    公开(公告)日:2014-06-17

    申请号:US13326020

    申请日:2011-12-14

    IPC分类号: H03D1/04

    CPC分类号: H04L25/0288 G06F13/4295

    摘要: Embodiments of an apparatus for signal conditioning, a serial data interface, and a method for a programmable delay filter are disclosed. In an embodiment of an apparatus for signal conditioning, a wave shaping circuit has a precursor signal, a post cursor signal, and a main signal combined to provide an output signal. The precursor signal, the post cursor signal, and the main signal are provided for combination independently of a clock signal. The main signal is delayed relative to the precursor signal, and the post cursor signal is delayed relative to the main signal.

    摘要翻译: 公开了用于信号调理的设备,串行数据接口和可编程延迟滤波器的方法的实施例。 在用于信号调理的装置的实施例中,波形整形电路具有前驱信号,后光标信号和组合以提供输出信号的主信号。 独立于时钟信号提供前体信号,后光标信号和主信号用于组合。 主信号相对于前驱信号延迟,后标光信号相对于主信号延迟。

    Serial link driver interface for a communication system
    4.
    发明授权
    Serial link driver interface for a communication system 有权
    用于通信系统的串行链路驱动程序接口

    公开(公告)号:US07915923B1

    公开(公告)日:2011-03-29

    申请号:US12400708

    申请日:2009-03-09

    IPC分类号: H03K19/0175

    CPC分类号: H04L25/0264

    摘要: Method and apparatus for a communication system (100) using a driver block (200) are described. The driver block includes memory having programmable non-volatile memory cells for storing configuration settings associated with operation of the driver block (200). The driver block (200) is programmable for a selected interface protocol for operation in an adaptive equalization mode to obtain an adaptive equalization value. The adaptive equalization value is stored as a fixed equalization value for operating the driver block in a fixed equalization mode. The driver block may be used as a serial link driver interface.

    摘要翻译: 描述使用驱动块(200)的通信系统(100)的方法和装置。 驱动器块包括具有用于存储与驱动器块(200)的操作相关联的配置设置的可编程非易失性存储器单元的存储器。 驱动器块(200)可编程为用于在自适应均衡模式下操作的选定接口协议以获得自适应均衡值。 自适应均衡值被存储为用于以固定均衡模式操作驱动器块的固定均衡值。 驱动程序块可以用作串行链路驱动程序接口。