公开(公告)号：US08254194B2

公开(公告)日：2012-08-28

申请号：US12911575

申请日：2010-10-25

申请人： Antonio Giambartino ,  Michele La Placa ,  Ignazio Martines

发明人： Antonio Giambartino ,  Michele La Placa ,  Ignazio Martines

IPC分类号： G11C7/02

CPC分类号： G11C7/067 ,  G11C7/04 ,  G11C16/28 ,  G11C2207/063

摘要： A reading circuit for a semiconductor memory, comprising: a circuital branch adapted to be electrically coupled to a bit line which is connected to a memory cell to be read; an evaluation circuit adapted to sense a cell electric current flowing through the bit line during a sensing phase of a reading operation of the data stored into the memory cell, the evaluation circuit comprising a negative feedback control loop adapted to control the potential of the bit line during the sensing phase, the control loop comprising a differential amplifier having an inverting input terminal operatively connected to the bit line, a non-inverting input terminal fed by a first reference potential, and a feedback circuital path connected between an output of the differential amplifier and the inverting input, wherein the feedback circuital path is adapted to conduct a measure current corresponding to the cell electric current, and comprises current/voltage conversion means for converting the measure current into a corresponding voltage. The conversion means of the feedback circuital path comprises at least one first transistor arranged to conduct the measure current, and biasing means adapted to bias the at least one first transistor so as to emulate the behavior of a resistor.

摘要翻译： 一种用于半导体存储器的读取电路，包括：电路分支，其适于电耦合到连接到要读取的存储器单元的位线; 评估电路，适于在存储在存储单元中的数据的读取操作的感测阶段期间感测流过位线的单元电流，该评估电路包括负反馈控制回路，适于控制位线的电位 在感测阶段期间，控制回路包括差分放大器，其具有可操作地连接到位线的反相输入端子，由第一参考电位馈送的非反相输入端子以及连接在差分放大器的输出端之间的反馈电路 和反相输入端，其中反馈电路路径适于传导对应于电池电流的测量电流，并且包括用于将测量电流转换成相应电压的电流/电压转换装置。 反馈电路的转换装置包括布置成传导测量电流的至少一个第一晶体管，以及适于偏置至少一个第一晶体管以便模拟电阻器的行为的偏置装置。

公开(公告)号：US20080013381A1

公开(公告)日：2008-01-17

申请号：US11713067

申请日：2007-02-28

申请人： Antonio Giambartino ,  Michele La Placa ,  Ignazio Martines

发明人： Antonio Giambartino ,  Michele La Placa ,  Ignazio Martines

IPC分类号： G11C11/4091 ,  H03F3/45

CPC分类号： G11C7/067 ,  G11C7/04 ,  G11C16/28 ,  G11C2207/063

摘要： A reading circuit for a semiconductor memory, comprising: a circuital branch adapted to be electrically coupled to a bit line which is connected to a memory cell to be read; an evaluation circuit adapted to sense a cell electric current flowing through the bit line during a sensing phase of a reading operation of the data stored into the memory cell, the evaluation circuit comprising a negative feedback control loop adapted to control the potential of the bit line during the sensing phase, the control loop comprising a differential amplifier having an inverting input terminal operatively connected to the bit line, a non-inverting input terminal fed by a first reference potential, and a feedback circuital path connected between an output of the differential amplifier and the inverting input, wherein the feedback circuital path is adapted to conduct a measure current corresponding to the cell electric current, and comprises current/voltage conversion means for converting the measure current into a corresponding voltage. The conversion means of the feedback circuital path comprises at least one first transistor arranged to conduct the measure current, and biasing means adapted to bias the at least one first transistor so as to emulate the behavior of a resistor.

摘要翻译： 一种用于半导体存储器的读取电路，包括：电路分支，其适于电耦合到连接到要读取的存储器单元的位线; 评估电路，适于在存储在存储单元中的数据的读取操作的感测阶段期间感测流过位线的单元电流，该评估电路包括负反馈控制回路，适于控制位线的电位 在感测阶段期间，控制回路包括差分放大器，其具有可操作地连接到位线的反相输入端子，由第一参考电位馈送的非反相输入端子以及连接在差分放大器的输出端之间的反馈电路 和反相输入端，其中反馈电路路径适于传导对应于电池电流的测量电流，并且包括用于将测量电流转换成相应电压的电流/电压转换装置。 反馈电路的转换装置包括布置成传导测量电流的至少一个第一晶体管，以及适于偏置至少一个第一晶体管以便模拟电阻器的行为的偏置装置。

公开(公告)号：US20070247903A1

公开(公告)日：2007-10-25

申请号：US11811394

申请日：2007-06-08

申请人： Ignazio Martines ,  Michele La Placa

发明人： Ignazio Martines ,  Michele La Placa

IPC分类号： G11C11/34

CPC分类号： G11C16/28

摘要： Described herein is a reading circuit for a nonvolatile memory device, wherein the currents flowing through an array memory cell to be read, and a reference memory cell with known contents, are converted into an array voltage and, respectively, into a reference voltage, which are compared to determine the contents of the array memory cell. The method envisages reducing the electrical stress to which the reference memory cell is subjected during reading, by generating and holding a sample of the reference voltage, then deselecting the reference memory cell, and then continuing reading using the sample of the reference voltage.

摘要翻译： 这里描述的是用于非易失性存储器件的读取电路，其中流过要读取的阵列存储单元的电流和具有已知内容的参考存储单元被转换成阵列电压并分别转换成参考电压， 进行比较以确定阵列存储单元的内容。 该方法设想通过产生和保持参考电压的样本，然后取消选择参考存储单元，然后使用参考电压的样本继续读取来减少读取期间参考存储单元所经历的电应力。

公开(公告)号：US07843738B2

公开(公告)日：2010-11-30

申请号：US11713067

申请日：2007-02-28

申请人： Antonio Giambartino ,  Michele La Placa ,  Ignazio Martines

发明人： Antonio Giambartino ,  Michele La Placa ,  Ignazio Martines

IPC分类号： G11C16/06

CPC分类号： G11C7/067 ,  G11C7/04 ,  G11C16/28 ,  G11C2207/063

摘要： A reading circuit for a semiconductor memory, comprising: a circuital branch adapted to be electrically coupled to a bit line which is connected to a memory cell to be read; an evaluation circuit adapted to sense a cell electric current flowing through the bit line during a sensing phase of a reading operation of the data stored into the memory cell, the evaluation circuit comprising a negative feedback control loop adapted to control the potential of the bit line during the sensing phase, the control loop comprising a differential amplifier having an inverting input terminal operatively connected to the bit line, a non-inverting input terminal fed by a first reference potential, and a feedback circuital path connected between an output of the differential amplifier and the inverting input, wherein the feedback circuital path is adapted to conduct a measure current corresponding to the cell electric current, and comprises current/voltage conversion means for converting the measure current into a corresponding voltage. The conversion means of the feedback circuital path comprises at least one first transistor arranged to conduct the measure current, and biasing means adapted to bias the at least one first transistor so as to emulate the behavior of a resistor.

摘要翻译： 一种用于半导体存储器的读取电路，包括：电路分支，其适于电耦合到连接到要读取的存储器单元的位线; 评估电路，适于在存储在存储单元中的数据的读取操作的感测阶段期间感测流过位线的单元电流，该评估电路包括负反馈控制回路，适于控制位线的电位 在感测阶段期间，控制回路包括差分放大器，其具有可操作地连接到位线的反相输入端子，由第一参考电位馈送的非反相输入端子以及连接在差分放大器的输出端之间的反馈电路 和反相输入端，其中反馈电路路径适于传导对应于电池电流的测量电流，并且包括用于将测量电流转换成相应电压的电流/电压转换装置。 反馈电路的转换装置包括布置成传导测量电流的至少一个第一晶体管，以及适于偏置至少一个第一晶体管以便模拟电阻器的行为的偏置装置。

公开(公告)号：US20080129256A1

公开(公告)日：2008-06-05

申请号：US11949517

申请日：2007-12-03

申请人： Michele La Placa ,  Ignazio Martines

发明人： Michele La Placa ,  Ignazio Martines

IPC分类号： G05F1/10 ,  G11C16/06

CPC分类号： G11C16/30 ,  G11C5/147

摘要： A voltage regulator including an output stage to generate an output voltage based upon a control voltage determined as a function of a difference between a reference voltage and a voltage representative of the output voltage. A sense resistor is coupled in series with the output stage and an auxiliary power stage is coupled in parallel with the output stage and cooperates therewith to supply a load as a function of a voltage drop across the sense resistor. A scaled replica stage of the output stage is controlled by the control voltage to generate a replica voltage of the output voltage. A bias network biases the scaled replica stage and output stage with identical currents to keep constant bias voltages. The output stage, the auxiliary power stage, the scaled replica stage, and the bias network each have high voltage transistors. The bias network is input with a square-wave control signal and an externally generated boosted voltage, to bias the scaled replica stage and the output stage in conduction states with the identical currents at the externally generated boosted voltage, when the square-wave control signal is active.

摘要翻译： 一种电压调节器，包括输出级，以根据基于参考电压和表示输出电压的电压之间的差值确定的控制电压来产生输出电压。 感测电阻器与输出级串联耦合，并且辅助功率级与输出级并联耦合，并与之配合以提供作为检测电阻器两端的电压降的函数的负载。 输出级的缩放级副本由控制电压控制，以产生输出电压的复制电压。 偏置网络以相同的电流偏置缩放的副本级和输出级，以保持恒定的偏置电压。 输出级，辅助功率级，缩放副本级和偏置网络均具有高压晶体管。 偏置网络输入方波控制信号和外部产生的升压电压，以便在方波控制信号时将外部产生的升压电压的相同电流偏置缩放的副本级和导通状态的输出级 活跃。

公开(公告)号：US07304505B2

公开(公告)日：2007-12-04

申请号：US11272847

申请日：2005-11-14

申请人： Michele La Placa ,  Ignazio Martines

发明人： Michele La Placa ,  Ignazio Martines

IPC分类号： H03K19/094

CPC分类号： H03K19/0013

摘要： The output buffer stage includes a half-bridge output stage having a first pair of complementary drivers connected in series between a supply line and a ground node, the high impedance state or conduction state of which is determined through a pair of control phases. The buffer stage includes a pair of switches controlled by the control phases, connected in series between them and connecting the transistors of the first stage in series. Each driver is connected in series with a switch, that is quickly opened to prevent under-threshold currents from circulating when the respective driver is turned off, and that is rapidly turned off when the respective driver is turned on.

摘要翻译： 输出缓冲级包括半桥输出级，其具有串联连接在电源线和接地节点之间的第一对互补驱动器，其高阻抗状态或导通状态通过一对控制相确定。 缓冲级包括由控制相位控制的一对开关，串联连接在一起，并连接第一级的晶体管。 每个驱动器与开关串联连接，快速打开，以防止相应驱动器关闭时低阈值电流循环，并且当相应驱动器打开时快速关闭。

公开(公告)号：US20070040562A1

公开(公告)日：2007-02-22

申请号：US11482524

申请日：2006-07-07

申请人： Michele La Placa ,  Ignazio Martines

发明人： Michele La Placa ,  Ignazio Martines

IPC分类号： G01R27/26

CPC分类号： H03K19/00384 ,  H03K17/167

摘要： A self-adaptive output buffer for an output terminal of an electronic circuit suitable to be connected to a load is proposed. The self-adaptive output buffer includes means for sensing an indication of the capacitance of the load and means for driving the load according to the sensing, wherein the means for sensing includes capacitive means with a preset capacitance, means for charging the capacitive means to a preset voltage, means for coupling the charged capacitive means with the load, and means for measuring a measuring voltage at the capacitive means due to a charge sharing between the capacitive means and the load.

摘要翻译： 提出了适用于连接到负载的电子电路的输出端的自适应输出缓冲器。 自适应输出缓冲器包括用于感测负载的电容的指示的装置和根据感测来驱动负载的装置，其中用于感测的装置包括具有预设电容的电容装置，用于将电容装置充电到 预置电压，用于将充电的电容性装置与负载耦合的装置，以及由于电容装置和负载之间的电荷共享而在电容装置处测量测量电压的装置。

公开(公告)号：US20070024123A1

公开(公告)日：2007-02-01

申请号：US11444287

申请日：2006-05-31

申请人： Michelangelo Pisasal ,  Vincenzo Sambataro ,  Maurizio Giabotti ,  Michele La Placa

发明人： Michelangelo Pisasal ,  Vincenzo Sambataro ,  Maurizio Giabotti ,  Michele La Placa

IPC分类号： H02M3/06

CPC分类号： G11C5/147 ,  G11C16/30

摘要： An architecture for implementing an integrated capacity advantageously includes a capacitive block inserted between a first and a second voltage reference. The block is formed from elementary capacitive modules. An enable block is inserted between the first voltage reference and the capacitive block and includes switches connected to the elementary capacitive modules and driven on their control terminals by control signals. Each switch of the enable block is inserted between the first voltage reference and a first end of a corresponding elementary capacitive module. A verify and enable circuit is connected to the first voltage reference, as well as at the input of the first end of the elementary capacitive modules and at the output of the control terminals of the switches of the enable block. The verify and enable circuit detects the presence of a current value in each of the elementary capacitive modules and, if said current is detected, disables that elementary capacitive module of the capacitive block using the corresponding switch of the enable block.

摘要翻译： 用于实现集成容量的架构有利地包括插入在第一和第二电压参考之间的电容性块。 该块由基本电容模块形成。 在第一电压基准和电容性块之间插入使能块，并且包括连接到基本电容模块并通过控制信号在其控制端子上驱动的开关。 使能块的每个开关插入在第一参考电压和对应的基本电容模块的第一端之间。 验证和使能电路连接到第一参考电压以及基本电容模块的第一端的输入端以及使能块的开关的控制端子的输出。 验证和使能电路检测每个基本电容模块中是否存在电流值，并且如果检测到所述电流，则使用使能块的相应开关禁用电容块的基本电容模块。

公开(公告)号：US07750688B2

公开(公告)日：2010-07-06

申请号：US12204084

申请日：2008-09-04

申请人： Michele La Placa ,  Ignazio Martines

发明人： Michele La Placa ,  Ignazio Martines

IPC分类号： H03B1/00 ,  H03K3/00

CPC分类号： H03K19/0013 ,  G11C7/1051 ,  G11C7/1057 ,  H03K19/01721 ,  H03K19/018571 ,  H03K19/09429 ,  Y10T29/49117

摘要： An output CMOS buffer includes MOS enhancement transistors and has a second complementary pair of natural or low threshold transistors, connected respectively in parallel to transistors of opposite type of conductivity of the complementary pair of enhancement MOS transistors of the final buffer stage. The gate terminals of the pair of natural or low threshold transistors are controlled by respective inverters, each supplied through a slew rate limiter of the slope of the driving current and are respectively connected between the positive supply node of the output buffer and a negative (below ground potential) node and between the common ground node of the output buffer and a positive supply node. The negative voltage and the positive voltage on the nodes are at least equal to the absolute value of the threshold voltage of the natural or low threshold transistors.

摘要翻译： 输出CMOS缓冲器包括MOS增强晶体管，并且具有与最终缓冲级的互补对的增强型MOS晶体管的相反类型的导电性的晶体管并联连接的自然或低阈值晶体管的第二互补对。 一对自然或低阈值晶体管的栅极端子由相应的反相器控制，每个反相器通过驱动电流的斜率的转换速率限制器提供，并分别连接在输出缓冲器的正供电节点和负极（下面） 接地电位）节点和输出缓冲器的公共接地节点和正电源节点之间。 节点上的负电压和正电压至少等于自然或低阈值晶体管的阈值电压的绝对值。

公开(公告)号：US07586331B2

公开(公告)日：2009-09-08

申请号：US11482524

申请日：2006-07-07

申请人： Michele La Placa ,  Ignazio Martines

发明人： Michele La Placa ,  Ignazio Martines

IPC分类号： H03K19/094 ,  H03K17/16 ,  H03B1/00

CPC分类号： H03K19/00384 ,  H03K17/167

摘要： A self-adaptive output buffer for an output terminal of an electronic circuit suitable to be connected to a load is proposed. The self-adaptive output buffer includes means for sensing an indication of the capacitance of the load and means for driving the load according to the sensing, wherein the means for sensing includes capacitive means with a preset capacitance, means for charging the capacitive means to a preset voltage, means for coupling the charged capacitive means with the load, and means for measuring a measuring voltage at the capacitive means due to a charge sharing between the capacitive means and the load.

摘要翻译： 提出了适用于连接到负载的电子电路的输出端的自适应输出缓冲器。 自适应输出缓冲器包括用于感测负载的电容的指示的装置和根据感测来驱动负载的装置，其中用于感测的装置包括具有预设电容的电容装置，用于将电容装置充电到 预置电压，用于将充电的电容装置与负载耦合的装置，以及由于电容装置和负载之间的电荷共享而在电容装置处测量测量电压的装置。