利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

74 条记录 (耗时 0.03 秒)

    MEMORY CELL PRESETTING FOR IMPROVED MEMORY PERFORMANCE
    3.
    发明申请
    MEMORY CELL PRESETTING FOR IMPROVED MEMORY PERFORMANCE 有权
    用于改善记忆性能的存储单元预置

    公开(公告)号：US20130013860A1

    公开(公告)日：2013-01-10

    申请号：US13619451

    申请日：2012-09-14

    申请人： Michele M. Franceschini ,  Ashish Jagmohan ,  John P. Karidis ,  Luis A. Lastras-Montano ,  Moinuddin K. Qureshi

    发明人： Michele M. Franceschini ,  Ashish Jagmohan ,  John P. Karidis ,  Luis A. Lastras-Montano ,  Moinuddin K. Qureshi

    IPC分类号： G06F12/00 ,  G06F12/08

    CPC分类号： G06F12/00 ,  G06F12/08 ,  G06F12/0802 ,  G06F12/0891

    摘要： Memory cell presetting for improved performance including a method for using a computer system to identify a region in a memory. The region includes a plurality of memory cells characterized by a write performance characteristic that has a first expected value when a write operation changes a current state of the memory cells to a desired state of the memory cells and a second expected value when the write operation changes a specified state of the memory cells to the desired state of the memory cells. The second expected value is closer than the first expected value to a desired value of the write performance characteristic. The plurality of memory cells in the region are set to the specified state, and the data is written into the plurality of memory cells responsive to the setting.

    摘要翻译： 用于改进性能的存储单元预设，包括使用计算机系统识别存储器中的区域的方法。 该区域包括多个存储单元，其特征在于当写入操作将存储单元的当前状态改变到存储单元的期望状态时具有第一期望值的写入性能特性，以及当写入操作改变时第二预期值 存储器单元的指定状态到存储器单元的期望状态。 第二期望值比第一期望值更接近写入性能特性的期望值。 区域中的多个存储单元被设置为指定状态，并且响应于该设置将数据写入多个存储单元。

    Memory cell presetting for improved memory performance
    5.
    发明授权
    Memory cell presetting for improved memory performance 有权
    内存单元预置，以提高内存性能

    公开(公告)号：US08874846B2

    公开(公告)日：2014-10-28

    申请号：US13619451

    申请日：2012-09-14

    申请人： Michele M. Franceschini ,  Ashish Jagmohan ,  John P. Karidis ,  Luis A. Lastras-Montano ,  Moinuddin K. Qureshi

    发明人： Michele M. Franceschini ,  Ashish Jagmohan ,  John P. Karidis ,  Luis A. Lastras-Montano ,  Moinuddin K. Qureshi

    IPC分类号： G06F12/00 ,  G06F12/08

    CPC分类号： G06F12/00 ,  G06F12/08 ,  G06F12/0802 ,  G06F12/0891

    摘要： Memory cell presetting for improved performance including a method for using a computer system to identify a region in a memory. The region includes a plurality of memory cells characterized by a write performance characteristic that has a first expected value when a write operation changes a current state of the memory cells to a desired state of the memory cells and a second expected value when the write operation changes a specified state of the memory cells to the desired state of the memory cells. The second expected value is closer than the first expected value to a desired value of the write performance characteristic. The plurality of memory cells in the region are set to the specified state, and the data is written into the plurality of memory cells responsive to the setting.

    摘要翻译： 用于改进性能的存储单元预设，包括使用计算机系统识别存储器中的区域的方法。 该区域包括多个存储单元，其特征在于当写入操作将存储单元的当前状态改变到存储单元的期望状态时具有第一期望值的写入性能特性，以及当写入操作改变时第二预期值 存储器单元的指定状态到存储器单元的期望状态。 第二期望值比第一期望值更接近写入性能特性的期望值。 区域中的多个存储单元被设置为指定状态，并且响应于该设置将数据写入多个存储单元。

    Encoding data into constrained memory
    7.
    发明授权
    Encoding data into constrained memory 失效
    将数据编码到受限内存中

    公开(公告)号：US08352839B2

    公开(公告)日：2013-01-08

    申请号：US12814142

    申请日：2010-06-11

    申请人： Michele M. Franceschini ,  Ashish Jagmohan ,  Luis A. Lastras-Montano ,  Mayank Sharma

    发明人： Michele M. Franceschini ,  Ashish Jagmohan ,  Luis A. Lastras-Montano ,  Mayank Sharma

    IPC分类号： H03M13/00

    CPC分类号： G11C13/0004 ,  G11C7/1006 ,  G11C13/00 ,  G11C13/0069

    摘要： Encoding data into constrained memory using a method for writing data that includes receiving write data to be encoded into a write word, receiving constraints on symbol values associated with the write word, encoding the write data into the write word, and writing the write word to a memory. The encoding includes: representing the write data and the constraints as a first linear system in a first field of a first size; embedding the first linear system into a second linear system in a second field of a second size, the second size larger than the first size; solving the second linear system in the second field resulting in a solution; and collapsing the solution into the first field resulting in the write word, the write word satisfying the constraints on symbol values associated with the write word.

    摘要翻译： 使用用于写入数据的方法将数据编码到约束存储器中，该方法包括接收要编码的写入数据到写入字中，接收与写入字相关联的符号值的约束，将写入数据编码到写入字中，以及将写入字写入 一个记忆 编码包括：在第一尺寸的第一场中表示作为第一线性系统的写入数据和约束; 在第二尺寸的第二场中将第一线性系统嵌入第二线性系统中，第二尺寸大于第一尺寸; 求解第二个场中的第二个线性系统，得到解决方案; 并且将解决方案折叠到第一场中，导致写入字，写入字满足与写入字相关联的符号值的约束。

    INCREASED CAPACITY HETEROGENEOUS STORAGE ELEMENTS
    8.
    发明申请
    INCREASED CAPACITY HETEROGENEOUS STORAGE ELEMENTS 有权
    增加容量异质存储元素

    公开(公告)号：US20120287714A1

    公开(公告)日：2012-11-15

    申请号：US13557298

    申请日：2012-07-25

    申请人： Ibrahim M. Elfadel ,  Michele M. Franceschini ,  Ashish Jagmohan ,  Luis A. Lastras-Montano ,  Mayank Sharma

    发明人： Ibrahim M. Elfadel ,  Michele M. Franceschini ,  Ashish Jagmohan ,  Luis A. Lastras-Montano ,  Mayank Sharma

    IPC分类号： G11C7/00 ,  G11C11/00 ,  G11C16/04

    CPC分类号： G11C29/08 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0076 ,  G11C2211/5641

    摘要： Providing increased capacity in heterogeneous storage elements including a method for reading from memory. The method includes receiving a read word from a block of memory cells, where physical characteristics of the memory cells support different sets of data levels. The read word is separated into two or more virtual read vectors. For each of the virtual read vectors, the codebook that was utilized to generate the virtual read vector is identified and a partial read data vector is generated. The generating includes multiplying the virtual read vector by a matrix that represents the codebook. The partial read data vectors are combined into a read message and the read message is output.

    摘要翻译： 在异构存储元件中提供增加的容量，包括从存储器读取的方法。 该方法包括从存储器单元块接收读取字，其中存储器单元的物理特性支持不同数据级的集合。 读取的字被分成两个或更多个虚拟读取向量。 对于每个虚拟读取向量，识别用于生成虚拟读取向量的码本，并生成部分读取数据向量。 生成包括将虚拟读取向量乘以代表码本的矩阵。 将部分读取数据矢量组合成读取消息，并输出读出的消息。

    Non-volatile memories with enhanced write performance and endurance
    9.
    发明授权
    Non-volatile memories with enhanced write performance and endurance 有权
    具有增强的写入性能和耐用性的非易失性存储器

    公开(公告)号：US08176235B2

    公开(公告)日：2012-05-08

    申请号：US12631505

    申请日：2009-12-04

    申请人： Michele M. Franceschini ,  Ashish Jagmohan ,  Luis A. Lastras-Montano ,  Mayank Sharma

    发明人： Michele M. Franceschini ,  Ashish Jagmohan ,  Luis A. Lastras-Montano ,  Mayank Sharma

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0246

    摘要： Enhanced write performance for non-volatile memories including a memory system that includes a receiver for receiving a data rate of a data sequence to be written to a non-volatile flash memory device. The memory system also includes a physical page selector for selecting a physical address of an invalid previously written memory page from a group of physical addresses of invalid previously written memory pages located on the non-volatile memory device, and for determining if the number of free bits in the invalid previously written memory page at the selected physical address is greater than or equal to the data rate. The memory system also includes a transmitter for outputting the selected physical address of the invalid previously written memory page, the outputting in response to the physical page selector determining that the number of free bits is greater than or equal to the data rate.

    摘要翻译： 对于非易失性存储器的增强的写入性能，包括存储器系统，该存储器系统包括用于接收要写入非易失性闪速存储器件的数据序列的数据速率的接收器。 存储器系统还包括物理页面选择器，用于从位于非易失性存储器设备上的无效的先前写入的存储器页面的一组物理地址中选择无效的先前写入的存储器页面的物理地址，并且用于确定是否有空闲数量 在所选物理地址处的无效的先前写入的存储器页中的位大于或等于数据速率。 存储器系统还包括用于输出无效的先前写入的存储器页面的所选物理地址的发射器，响应于物理页选择器确定空闲位的数量大于或等于数据速率的输出。

    NON-VOLATILE MEMORIES WITH ENHANCED WRITE PERFORMANCE AND ENDURANCE
    10.
    发明申请
    NON-VOLATILE MEMORIES WITH ENHANCED WRITE PERFORMANCE AND ENDURANCE 有权
    具有增强的写性能和耐用性的非易失性存储器

    公开(公告)号：US20110138105A1

    公开(公告)日：2011-06-09

    申请号：US12631505

    申请日：2009-12-04

    申请人： Michele M. Franceschini ,  Ashish Jagmohan ,  Luis A. Lastras-Montano ,  Mayank Sharma

    发明人： Michele M. Franceschini ,  Ashish Jagmohan ,  Luis A. Lastras-Montano ,  Mayank Sharma

    IPC分类号： G06F12/02 ,  G06F12/00

    CPC分类号： G06F12/0246

    摘要： Enhanced write performance for non-volatile memories including a memory system that includes a receiver for receiving a data rate of a data sequence to be written to a non-volatile flash memory device. The memory system also includes a physical page selector for selecting a physical address of an invalid previously written memory page from a group of physical addresses of invalid previously written memory pages located on the non-volatile memory device, and for determining if the number of free bits in the invalid previously written memory page at the selected physical address is greater than or equal to the data rate. The memory system also includes a transmitter for outputting the selected physical address of the invalid previously written memory page, the outputting in response to the physical page selector determining that the number of free bits is greater than or equal to the data rate.

    摘要翻译： 对于非易失性存储器的增强的写入性能，包括存储器系统，该存储器系统包括用于接收要写入非易失性闪速存储器件的数据序列的数据速率的接收器。 存储器系统还包括物理页面选择器，用于从位于非易失性存储器设备上的无效的先前写入的存储器页面的一组物理地址中选择无效的先前写入的存储器页面的物理地址，并且用于确定是否有空闲数量 在所选物理地址处的无效的先前写入的存储器页中的位大于或等于数据速率。 存储器系统还包括用于输出无效的先前写入的存储器页面的所选物理地址的发射器，响应于物理页选择器确定空闲位的数量大于或等于数据速率的输出。