公开(公告)号：US20120105115A1

公开(公告)日：2012-05-03

申请号：US13344201

申请日：2012-01-05

申请人： Michiyo YAMAMOTO ,  Kenji Murata ,  Kazuya Hatooka

发明人： Michiyo YAMAMOTO ,  Kenji Murata ,  Kazuya Hatooka

IPC分类号： H03L7/06

CPC分类号： H04L7/0337 ,  H03L7/091 ,  H03L7/0996

摘要： A clock and data recovery circuit includes a multiphase clock generator circuit which generates a multiphase clock having a plurality of clocks, a sampling circuit which samples a received data signal transferring serial data in synchronism with each of the plurality of clocks, and generates a plurality of data signals, a data recovery unit which generates a selection signal indicating a data signal having an appropriate phase among the plurality of data signals, and a storage unit which stores the selection signal. The data recovery unit selects one of the plurality of data signals, based on the selection signal read from the storage unit, and a clock corresponding to the selected data signal.

摘要翻译： 时钟和数据恢复电路包括产生具有多个时钟的多相时钟的多相时钟发生器电路，采样电路，对与多个时钟中的每个时钟同步地传送串行数据的接收数据信号进行采样，并产生多个 数据信号，数据恢复单元，其生成指示在多个数据信号中具有适当相位的数据信号的选择信号;以及存储单元，存储选择信号。 数据恢复单元基于从存储单元读取的选择信号和对应于所选择的数据信号的时钟来选择多个数据信号中的一个。