公开(公告)号：US20110169578A1

公开(公告)日：2011-07-14

申请号：US13119289

申请日：2009-09-11

申请人： Mickael Lucas ,  Emeric Uguen

发明人： Mickael Lucas ,  Emeric Uguen

IPC分类号： H03L7/06

CPC分类号： H03L7/1976

摘要： A signal processing module with a timing comparator such as a time to digital converter is provided. The module may be part of a phase locked loop with a fractional frequency divider that acts to produce a divided down signal modulated with jitter in its timing. The timing comparator comprises an error cancellation stage (30, 24.1, 2060) to remove a predicted effect of the imparted jitter from the timing comparator output signal. A jitter detector (80, 1046, 2064) is used to detect the jitter from the comparator output signal, preferably residual jitter after the predicted effect of the jitter has been removed. Synchronous detection, such as correlation with the predicted jitter may be used to detect the jitter. The jitter detector (80, 1046, 2064) adjusts a calibration factor of the timing comparator dependent on the detected jitter. Adjustment of the calibration factor may involve adjustment of a reference time delay defined by a time delay element in a time to digital converter, application of a calibration factor to the result of timing comparison or application of a calibration factor to the predicted jitter.

摘要翻译： 提供了具有诸如时间到数字转换器的定时比较器的信号处理模块。 模块可以是具有分数分频器的锁相环的一部分，其用于产生在其定时中以抖动调制的分频信号。 定时比较器包括消除由定时比较器输出信号引起的抖动的预测影响的误差消除级（30,24.1,2060）。 抖动检测器（80,1046,2064）用于检测来自比较器输出信号的抖动，优选地，抖动预测的影响已经消除之后的残余抖动。 可以使用诸如与预测抖动的相关性的同步检测来检测抖动。 抖动检测器（80,1046,2064）根据检测到的抖动来调整定时比较器的校准因子。 校准因子的调整可以包括调整由数字转换器中的时间延迟元件定义的参考时间延迟，将校准因子应用于定时比较的结果或将校准因子应用于预测的抖动。

公开(公告)号：US08441323B2

公开(公告)日：2013-05-14

申请号：US13119289

申请日：2009-09-11

申请人： Mickael Lucas ,  Emeric Uguen

发明人： Mickael Lucas ,  Emeric Uguen

IPC分类号： H03L7/095

CPC分类号： H03L7/1976

摘要： A signal processing module with a timing comparator such as a time to digital converter is provided. The timing comparator comprises an error cancellation stage to remove a predicted effect of the imparted jitter from the timing comparator output signal. A jitter detector is used to detect the jitter from the comparator output signal, preferably residual jitter after the predicted effect of the jitter has been removed. Synchronous detection, such as correlation with the predicted jitter may be used to detect the jitter. The jitter detector adjusts a calibration factor of the timing comparator dependent on the detected jitter.

摘要翻译： 提供了具有诸如时间到数字转换器的定时比较器的信号处理模块。 定时比较器包括误差消除级，以消除来自定时比较器输出信号的被施加抖动的预测效果。 使用抖动检测器来检测来自比较器输出信号的抖动，优选地，抖动预测的影响已经消除之后的残余抖动。 可以使用诸如与预测抖动的相关性的同步检测来检测抖动。 抖动检测器根据检测到的抖动来调整定时比较器的校准因子。

公开(公告)号：US08804289B2

公开(公告)日：2014-08-12

申请号：US12682746

申请日：2008-10-13

申请人： Denis Crespo ,  Herve Marie ,  Nguyen Trieu Luan Le ,  Mickael Lucas

发明人： Denis Crespo ,  Herve Marie ,  Nguyen Trieu Luan Le ,  Mickael Lucas

IPC分类号： H02H9/04

CPC分类号： H01L27/0266 ,  H01L27/0259 ,  H02H9/046

摘要： A protection circuit (100, 700) is disclosed for protecting an integrated circuit having a first supply rail (Vcc) and a second supply rail (Vss) from exposure to an excessive voltage. The protection circuit (100, 700) comprises a sensor (120) for sensing a voltage increase on the first supply rail (Vcc). Such a sensor may be implemented as an RC element. The sensor (120) has an output coupled to a signal path for providing a detection signal on said path. The sensor (120) triggers a clamping circuit (180) to clamp the first supply rail (Vcc) to the second supply rail (Vss) in response to the detection signal, which typically signals an ESD event on the supply rails. A pre-amplifying stage (160) is coupled between the sensor (120) and the clamping circuit (180) to amplify the detection signal for the clamping circuit (180). The protection circuit further comprises a hold circuit (140) for holding the control input of the pre-amplifying stage (160) in an enabled state upon termination of the detection signal. Such a hold circuit may comprise a further RC element for accelerating the activation of the clamping circuit (180) and extending the activation of the clamping circuit beyond the termination of the detection signal, thus yielding a more efficient protection circuit (100, 700).

摘要翻译： 公开了一种用于保护具有第一电源轨（Vcc）和第二电源轨（Vss）的集成电路不被暴露于过电压的保护电路（100,700）。 保护电路（100,700）包括用于感测第一电源轨（Vcc）上的电压增加的传感器（120）。 这样的传感器可以被实现为RC元件。 传感器（120）具有耦合到信号路径的输出，用于在所述路径上提供检测信号。 响应于检测信号，传感器（120）触发钳位电路（180）将第一电源轨（Vcc）钳位到第二电源轨（Vss），该检测信号通常表示电源轨上的ESD事件。 预放大级（160）耦合在传感器（120）和钳位电路（180）之间，以放大钳位电路（180）的检测信号。 保护电路还包括保持电路（140），用于在检测信号终止时将预放大级（160）的控制输入保持在使能状态。 这种保持电路可以包括用于加速钳位电路（180）的激活并且将钳位电路的激活延伸超过检测信号的终止的另外的RC元件，从而产生更有效的保护电路（100,700）。

公开(公告)号：US20100214706A1

公开(公告)日：2010-08-26

申请号：US12682746

申请日：2008-10-13

申请人： Denis Crespo ,  Herve Marie ,  Nguyen Trieu Luan Le ,  Mickael Lucas

发明人： Denis Crespo ,  Herve Marie ,  Nguyen Trieu Luan Le ,  Mickael Lucas

IPC分类号： H02H9/04

CPC分类号： H01L27/0266 ,  H01L27/0259 ,  H02H9/046

摘要： A protection circuit (100, 700) is disclosed for protecting an integrated circuit having a first supply rail (Vcc) and a second supply rail (Vss) from exposure to an excessive voltage. The protection circuit (100, 700) comprises a sensor (120) for sensing a voltage increase on the first supply rail (Vcc). Such a sensor may be implemented as an RC element. The sensor (120) has an output coupled to a signal path for providing a detection signal on said path. The sensor (120) triggers a clamping circuit (180) to clamp the first supply rail (Vcc) to the second supply rail (Vss) in response to the detection signal, which typically signals an ESD event on the supply rails. A pre-amplifying stage (160) is coupled between the sensor (120) and the clamping circuit (180) to amplify the detection signal for the clamping circuit (180). The protection circuit further comprises a hold circuit (140) for holding the control input of the pre-amplifying stage (160) in an enabled state upon termination of the detection signal. Such a hold circuit may comprise a further RC element for accelerating the activation of the clamping circuit (180) and extending the activation of the clamping circuit beyond the termination of the detection signal, thus yielding a more efficient protection circuit (100, 700).

摘要翻译： 公开了一种用于保护具有第一电源轨（Vcc）和第二电源轨（Vss）的集成电路不被暴露于过电压的保护电路（100,700）。 保护电路（100,700）包括用于感测第一电源轨（Vcc）上的电压增加的传感器（120）。 这样的传感器可以被实现为RC元件。 传感器（120）具有耦合到信号路径的输出，用于在所述路径上提供检测信号。 响应于检测信号，传感器（120）触发钳位电路（180）将第一电源轨（Vcc）钳位到第二电源轨（Vss），该检测信号通常表示电源轨上的ESD事件。 预放大级（160）耦合在传感器（120）和钳位电路（180）之间，以放大钳位电路（180）的检测信号。 保护电路还包括保持电路（140），用于在检测信号终止时将预放大级（160）的控制输入保持在使能状态。 这种保持电路可以包括用于加速钳位电路（180）的激活并且将钳位电路的激活延伸超过检测信号的终止的另外的RC元件，从而产生更有效的保护电路（100,700）。