公开(公告)号：US20190113568A1

公开(公告)日：2019-04-18

申请号：US15785792

申请日：2017-10-17

Applicant: Microchip Technology Incorporated

Inventor： Stephen Bowling ,  Igor Wojewoda ,  Dereck Fernandes ,  Manivannan Balu ,  Yong Yuenyongsgool ,  Timothy Phoenix ,  Steve Bradley

IPC: G01R31/317 ,  G01R31/3177

CPC classification number: G01R31/31724 ,  G01R31/31723 ,  G01R31/3177 ,  G11C29/14 ,  G11C29/26 ,  G11C29/48 ,  G11C2029/0401 ,  G11C2029/0409

Abstract: In an embedded device with a plurality of processor cores, each core has a static random access memory (SRAM), a memory built-in self-test (MBIST) controller associated with the SRAM, an MBIST access port coupled with the MBIST controller, an MBIST finite state machine (FSM) coupled with the MBIST access port via a first multiplexer, and a JTAG interface coupled with the MBIST access ports of each processor core via the multiplexer of each processor core.

公开(公告)号：US10352998B2

公开(公告)日：2019-07-16

申请号：US15785792

申请日：2017-10-17

Applicant: Microchip Technology Incorporated

Inventor： Stephen Bowling ,  Igor Wojewoda ,  Dereck Fernandes ,  Manivannan Balu ,  Yong Yuenyongsgool ,  Timothy Phoenix ,  Steve Bradley

IPC: G01R31/317 ,  G01R31/3177 ,  G06F15/80 ,  G11C29/14 ,  G11C29/26 ,  G11C29/48 ,  G11C29/04

Abstract: In an embedded device with a plurality of processor cores, each core has a static random access memory (SRAM), a memory built-in self-test (MBIST) controller associated with the SRAM, an MBIST access port coupled with the MBIST controller, an MBIST finite state machine (FSM) coupled with the MBIST access port via a first multiplexer, and a JTAG interface coupled with the MBIST access ports of each processor core via the multiplexer of each processor core.